Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 44
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A23 A22 A21 A20 A19 A18 A17 A16
76543210
Mnemonic: DMAP5_TAR_1 Address: FF86h
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A31 A30 A29 A28 A27 A26 A25 A24
76543210
Mnemonic: DMAP5_TAR_2 Address: FF87h
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A15 A14 A13 A12 A11 A10 A9 A8
76543210
Mnemonic: DMAP5_SRC Address: FF88h
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- SIZE4 SIZE3 SIZE2 SIZE1 SIZE0- ENBL
76543210
Mnemonic: DMAP5_CTL Address: FF89h
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Data mapper D3 has the highest data mapping
priority. The configuration registers (CRU) are al-
ways accessible by the microcontroller. D3 has
two selectable sizes of 4K and 256 bytes. Follow-
ing a system reset, the D3 block size is set to 4K
bytes and occupies the upper 4K bytes of the logi-
cal data space, between addresses F000h and
FFFFh, inclusive. At the end of the initialization
program, the D3 data mapper zone is reduced to
256 bytes to conserve address space.
D3 start address must be aligned to 4K address
boundaries. All mapper registers are accessible
through D3. The D3 mapper is always enabled.
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A31 A30 A29 A28 A27 A26 A25 A24
76543210
Mnemonic: DMAP3_TAR Address: FF19h
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- - - - A15 A14 A13 A12
76543210
Mnemonic: DMAP3_SRC Address: FF1Ah
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- - - - - --
76543210
BLOCK
SIZE
Mnemonic: DMAP3_CTL Address: FF1Bh
When set, BLOCKSIZE defines the D3 mapper
block size to 4K bytes. The BLOCKSIZE bit is set
automatically at power-up. When cleared, the
block size is reduced to 256 bytes.
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A Zylogic configurable system-on-chip user can
create custom microcontroller “soft” modules using
the on-chip Configurable System Logic (CSL) ma-
trix. These “soft” modules can be mapped into the
8032’s external data memory (XDATA) or into SFR
space. If a CSL “soft” module is mapped into SFR
space, then any control registers implemented in
the CSL replace locations within the 8032’s SFR
memory. The fully programmable SFR export
mapper supplies a 32-bit address on the CSI bus
whenever an external SFR access is detected.
Following a System Reset event, this mapper is
disabled. The SFR export mapper has a special
programmable register called XMAP_ALT. The
content of XMAP_ALT or XMAP_TAR_2 is placed
on the A31-A24 CSI bus address lines when a
latch or a pin instruction occurs, respectively, dur-
ing an external SFR access event. This feature
can be useful in debugging sessions to discrimi-
nate between various SFR instructions.
Overall, there are 128 SFR-addressable locations
in an 8032 microcontroller. Table 30 describes the
SFRs within the MCU's scratchpad RAM. The Zy-
logic FastChip development software prevents at-
tempts to place CSL “soft” modules on internal
SFR addresses already used by the MCU.
The translated address, when accessing an ex-
ported SFRs, consists of the XMAP_TAR_2 or
XMAP_ALT register, the XMAP_TAR_1 register,
and the XMAP_TAR_0 register appended to the
A[7:0] address from the 8032 MCU.
“Soft” modules with exported SFR registers can
also be accessed via 8032 external-memory refer-
ences, using the values loaded into the data map-
pers. Placing “soft” module registers in the 8032’s
SFR address space allows faster and simpler ac-
cess using direct reference instructions. This
method also enables the application code to use
bit-manipulating instructions on these registers.
Application code usually never modifies the SFR
export mapper registers. The register values are
set during initialization.
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A15 A14A13A12A11A10 A9 A8
76543210
Mnemonic: XMAP_TAR_0 Address: FE20h
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A23 A22A21A20A19A18A17A16
76543210