Specifications

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The D0 mapper has one programmable CRU reg-
ister, DMAP0_TAR. The content of DMAP0_TAR
is placed on the A[31:24] physical CSI bus address
lines when a D0 matching event occurs. D0 is al-
ways enabled.
D
D
0
0
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
(
(
R
R
A
A
M
M
m
m
a
a
p
p
p
p
e
e
r
r
)
)
A31 A30 A29 A28 A27 A26 A25 A24
76543210
Mnemonic: DMAP0_TAR Address: FF0Eh
D
D
1
1
,
,
D
D
2
2
,
,
D
D
4
4
,
,
D
D
5
5
–
–
F
F
u
u
l
l
l
l
y
y
p
p
r
r
o
o
g
g
r
r
a
a
m
m
m
m
a
a
b
b
l
l
e
e
d
d
a
a
t
t
a
a
m
m
a
a
p
p
-
-
p
p
e
e
r
r
s
s
Data mapper D5 has higher priority in case of an
address overlap with D4, D2, D1 or D0. Mappers
D5, D4, D2, and D1 can be individually enabled
and are disabled after a System Reset event. The
Zylogic initialization program assigns application
dependent values to these mappers. The user can
modify these assignments by writing different val-
ues to the corresponding mapper registers.
D
D
1
1
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
(
(
L
L
o
o
w
w
B
B
y
y
t
t
e
e
)
)
A15 A14 A13 A12 A11 A10 A9 A8
76543210
Mnemonic: DMAP1_TAR_0 Address: FF0Fh
D
D
1
1
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
(
(
M
M
i
i
d
d
B
B
y
y
t
t
e
e
)
)
A23 A22 A21 A20 A19 A18 A17 A16
76543210
Mnemonic: DMAP1_TAR_1 Address: FF10h
D
D
1
1
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
(
(
H
H
i
i
g
g
h
h
B
B
y
y
t
t
e
e
)
)
A31 A30 A29 A28 A27 A26 A25 A24
76543210
Mnemonic: DMAP1_TAR_2 Address: FF11h
D
D
1
1
Z
Z
o
o
n
n
e
e
S
S
o
o
u
u
r
r
c
c
e
e
A
A
d
d
d
d
r
r
e
e
s
s
s
s
A15 A14 A13 A12 A11 A10 A9 A8
76543210
Mnemonic: DMAP1_SRC Address: FF12h
D
D
1
1
C
C
o
o
n
n
t
t
r
r
o
o
l
l
- SIZE4 SIZE3 SIZE2 SIZE1 SIZE0- ENBL
76543210
Mnemonic: DMAP1_CTL Address: FF13h
D
D
2
2
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
(
(
L
L
o
o
w
w
B
B
y
y
t
t
e
e
)
)
A15 A14 A13 A12 A11 A10 A9 A8
76543210
Mnemonic: DMAP2_TAR_0 Address: FF14h
D
D
2
2
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
(
(
M
M
i
i
d
d
B
B
y
y
t
t
e
e
)
)
A23 A22A21A20A19A18A17A16
76543210
Mnemonic: DMAP2_TAR_1 Address: FF15h
D
D
2
2
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
(
(
H
H
i
i
g
g
h
h
B
B
y
y
t
t
e
e
)
)
A31 A30A29A28A27A26A25A24
76543210
Mnemonic: DMAP2_TAR_2 Address: FF16h
D
D
2
2
Z
Z
o
o
n
n
e
e
S
S
o
o
u
u
r
r
c
c
e
e
A
A
d
d
d
d
r
r
e
e
s
s
s
s
A15 A14A13A12A11A10 A9 A8
76543210
Mnemonic: DMAP2_SRC Address: FF17h
D
D
2
2
C
C
o
o
n
n
t
t
r
r
o
o
l
l
- SIZE4 SIZE3 SIZE2 SIZE1 SIZE0- ENBL
76543210
Mnemonic: DMAP2_CTL Address: FF18h
D
D
4
4
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
(
(
L
L
o
o
w
w
B
B
y
y
t
t
e
e
)
)
A15 A14A13A12A11A10 A9 A8
76543210
Mnemonic: DMAP4_TAR_0 Address: FF80h
D
D
4
4
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
(
(
M
M
i
i
d
d
B
B
y
y
t
t
e
e
)
)
A23 A22A21A20A19A18A17A16
76543210
Mnemonic: DMAP4_TAR_1 Address: FF81h
D
D
4
4
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
(
(
H
H
i
i
g
g
h
h
B
B
y
y
t
t
e
e
)
)
A31 A30A29A28A27A26A25A24
76543210
Mnemonic: DMAP4_TAR_2 Address: FF82h
D
D
4
4
Z
Z
o
o
n
n
e
e
S
S
o
o
u
u
r
r
c
c
e
e
A
A
d
d
d
d
r
r
e
e
s
s
s
s
A15 A14A13A12A11A10 A9 A8
76543210
Mnemonic: DMAP4_SRC Address: FF83h
D
D
4
4
C
C
o
o
n
n
t
t
r
r
o
o
l
l
- SIZE4 SIZE3 SIZE2 SIZE1 SIZE0- ENBL
76543210
Mnemonic: DMAP4_CTL Address: FF84h
D
D
5
5
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
(
(
L
L
o
o
w
w
B
B
y
y
t
t
e
e
)
)
A15 A14A13A12A11A10 A9 A8
76543210
Mnemonic: DMAP5_TAR_0 Address: FF85h