Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 42
C
C
1
1
,
,
C
C
2
2
–
–
F
F
u
u
l
l
l
l
y
y
p
p
r
r
o
o
g
g
r
r
a
a
m
m
m
m
a
a
b
b
l
l
e
e
c
c
o
o
d
d
e
e
m
m
a
a
p
p
p
p
e
e
r
r
s
s
Code mapper C2 has the highest priority in case of
an address overlap with other code mappers. C1
and C2 can be individually enabled. Following a
system reset, mappers C1 and C2 are disabled.
Mapper C0 is always enabled. The Zylogic initiali-
zation program assigns application dependent val-
ues to these mappers. The user can modify these
assignments by writing different values to the cor-
responding mapper registers.
C
C
1
1
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
(
(
L
L
o
o
w
w
B
B
y
y
t
t
e
e
)
)
A15 A14 A13 A12 A11 A10 A9 A8
76543210
Mnemonic: CMAP1_TAR_0 Address: FF02h
C
C
1
1
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
(
(
M
M
i
i
d
d
B
B
y
y
t
t
e
e
)
)
A23 A22 A21 A20 A19 A18 A17 A16
76543210
Mnemonic: CMAP1_TAR_1 Address: FF03h
C
C
1
1
O
O
p
p
e
e
r
r
a
a
n
n
d
d
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
A31 A30 A29 A28 A27 A26 A25 A24
76543210
Mnemonic: CMAP1_TAR_2 Address: FF04h
C
C
1
1
O
O
p
p
-
-
C
C
o
o
d
d
e
e
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
A31 A30 A29 A28 A27 A26 A25 A24
76543210
Mnemonic: CMAP1_ALT Address: FF07h
C
C
1
1
Z
Z
o
o
n
n
e
e
S
S
o
o
u
u
r
r
c
c
e
e
A
A
d
d
d
d
r
r
e
e
s
s
s
s
A15 A14 A13 A12 A11 A10 A9 A8
76543210
Mnemonic: CMAP1_SRC Address: FF05h
C
C
1
1
C
C
o
o
n
n
t
t
r
r
o
o
l
l
- SIZE4 SIZE3 SIZE2 SIZE1 SIZE0- ENBL
76543210
Mnemonic: CMAP1_CTL Address: FF06h
C
C
2
2
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
(
(
L
L
o
o
w
w
B
B
y
y
t
t
e
e
)
)
A15 A14 A13 A12 A11 A10 A9 A8
76543210
Mnemonic: CMAP2_TAR_0 Address: FF08h
C
C
2
2
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
(
(
M
M
i
i
d
d
B
B
y
y
t
t
e
e
)
)
A23 A22 A21 A20 A19 A18 A17 A16
76543210
Mnemonic: CMAP2_TAR_1 Address: FF09h
C
C
2
2
O
O
p
p
e
e
r
r
a
a
n
n
d
d
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
A31 A30A29A28A27A26A25A24
76543210
Mnemonic: CMAP2_TAR_2 Address: FF0Ah
C
C
2
2
O
O
p
p
-
-
C
C
o
o
d
d
e
e
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
A31 A30A29A28A27A26A25A24
76543210
Mnemonic: CMAP2_ALT Address: FF0Dh
C
C
2
2
Z
Z
o
o
n
n
e
e
S
S
o
o
u
u
r
r
c
c
e
e
A
A
d
d
d
d
r
r
e
e
s
s
s
s
A15 A14A13A12A11A10 A9 A8
76543210
Mnemonic: CMAP2_SRC Address: FF0Bh
C
C
2
2
C
C
o
o
n
n
t
t
r
r
o
o
l
l
- SIZE4 SIZE3 SIZE2 SIZE1 SIZE0- ENBL
76543210
Mnemonic: CMAP2_CTL Address: FF0Ch
D
D
a
a
t
t
a
a
m
m
a
a
p
p
p
p
e
e
r
r
s
s
Data mappers perform address translations on
data access instructions. There are six data map-
pers as shown in Table 22. D0 maps accesses to
the internal system SRAM. D1, D2, D4, and D5
are fully programmable and D3 maps the CRU
configuration registers.
Table 22. Data Mappers.
Mapper Priority Enable
D3 (CRU) 1 Always Enabled
D5 2 Optional
D4 3 Optional
D2 4 Optional
D1 5 Optional
D0 (RAM) 6 Always Enabled
D
D
0
0
–
–
R
R
A
A
M
M
d
d
a
a
t
t
a
a
m
m
a
a
p
p
p
p
e
e
r
r
The D0 has the lowest data mapping priority. The
internal system RAM is always accessible by the
microcontroller in data space following a System
Reset. The size and configuration of the internal
system RAM is device dependent.
For example, the RAM in the ZE520 has a fixed
size of 40K bytes. The bottom 32K bytes reside in
data locations 0000h – 7FFFh. Four copies of the
top 8K bytes appear at data locations 8000h,
A000h, C000h and E000h, unless another data
mapper is enabled and re-uses these locations.
If enabled, data mappers D1 and D2 override RAM
data space. The D3 mapper, used to access the
configuration registers (CRU) always overrides the
other mappers, as explained below.