Specifications

41 www.zylogic.com.cn
The block size results in a mask used during ad-
dress matching. The block size is specified as the
log base two of the desired address zone size, in
bytes. The mask is a result of the following calcu-
lation.
12
_
−=
SizeBlock
Mask
The lower 8 bits of the logical address are not part
of the comparison. A block size must be in the
range between 256 and 64K. Consequently, the
block size value must be between 8 and 16, inclu-
sive.
Various system resources occupy non-contiguous
address spaces in the 4G-byte address space
available through the CSI bus. The Zylogic Fast-
Chip development system automatically creates a
16M-byte memory map as shown in Table 20 and
Figure 35. The memory map is 16M bytes instead
of the full 4G bytes because the upper eight bits of
the physical address are assigned to the values
shown in Table 23 to aid in debugging.
C
C
o
o
d
d
e
e
m
m
a
a
p
p
p
p
e
e
r
r
s
s
Code mappers perform address translations on
code fetches. There are three code mappers, in-
cluding a dedicated code mapper for the initializa-
tion program stored in on-chip ROM plus two fully
programmable code mappers. The code mappers
are listed in Table 21.
Table 21. Code Mappers.
Mapper Priority Enable
C2 1 Optional
C1 2 Optional
C0 (ROM) 3 Always Enabled
C
C
0
0
–
–
R
R
O
O
M
M
c
c
o
o
d
d
e
e
m
m
a
a
p
p
p
p
e
e
r
r
The C0 mapper has the lowest priority. The inter-
nal ROM is always accessible by the microcontrol-
ler following a System Reset event. The ROM size
is fixed at 1K byte, implemented with 64 copies
that are available in the program space. The cop-
ies are repeated at every 1K byte boundary in
code space.
At the end of the initialization program, the other
two code mappers, C1 and C2, can be pro-
grammed to override the ROM code mapper.
The C0 mapper has two programmable registers:
CMAP0_TAR and CMAP0_ALT, both residing in
the CRU. During a C0 address-matching event,
the content of the CMAP0_TAR or CMAP0_ALT
register is placed on the A[31:24] physical CSI bus
address lines whenever an operand or an op-code
fetch occurs, respectively. This feature is useful in
debugging sessions to discriminate between op-
code or operand fetches. C0 is always enabled.
C
C
0
0
O
O
p
p
e
e
r
r
a
a
n
n
d
d
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
(
(
R
R
O
O
M
M
m
m
a
a
p
p
p
p
e
e
r
r
)
)
A31 A30A29A28A27A26A25A24
76543210
Mnemonic: CMAP0_TAR Address: FF00h
C
C
0
0
O
O
p
p
-
-
C
C
o
o
d
d
e
e
T
T
a
a
r
r
g
g
e
e
t
t
A
A
d
d
d
d
r
r
e
e
s
s
s
s
(
(
R
R
O
O
M
M
M
M
a
a
p
p
p
p
e
e
r
r
)
)
A31 A30A29A28A27A26A25A24
76543210
Mnemonic: CMAP0_ALT Address: FF01h
Table 20. Addresses Allocated to System Resources.
CSI physical
address space
8032
Address
zone (bytes) Description Notes
0 – 0xFFFF 1K Internal ROM Accessible following a system reset
0x1_0000 –
0x1_FFFF
Depends on
device
Internal XDATA RAM
ZE502=8K, ZE505=16K,
ZE512=32K, ZE520=40K,
ZE532=64K
0x2_0000 –
0x02_FFFF
256 or
4K
CRU – system configuration
registers
0x3_0000 –
0x7_FFFF
N.A. Reserved Debugger access only
0x10_0000 –
0x7F_FFFF
User-defined
(*)
CSL “soft” modules, external
devices, external memories,
and exported SFRs.
External devices or memories other
than the one connected to CE- out-
put pin should use this address
space also.
0x80_0000 –
0xFF_FFFF
<= 64K External Memory Connected via the MIU port