Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
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A[7:0]A[15:8]
8032 Logical Address
ZONE
BLOCK SIZE
ENABLE
=
A[31:0]
CSI Bus Physical Address
Mask = 2
BLOCK_SIZE
- 1
Target Address[23:0]
Translate
Generated Mask
Figure 36. Address mapper conceptual block
diagram.
Figure 36 shows a generalized block diagram of
how an address mapper translates an 8032 logic
address into a physical address displayed on the
CSI bus.
When the MCU presents an address, the appro-
priate mapper tracks the type of operation. A code
mapper only responds to code accesses, a data
mapper only responds to data accesses, and so
on. The block size defines how many lower ad-
dress bits are ignored when comparing the MCU’s
logic address and the target address zone. Be-
cause all zones must be equal to 256 bytes or lar-
ger, the lower eight bits of the generated mask can
be ignored during the comparison. The mapper
then compares the upper 8 bits of the logical ad-
dress with the 8 bits of the zone target address
and masks off any locations indicated with the
BLOCK_SIZE value. If the mapper is enabled and
the two addresses compare, then the mapper pre-
sents the translated address on the CSI bus. The
lower physical address bits consists of the masked
bits from the logical address, A[15:0]. Because all
zones are 256 bytes or larger, the lower-byte of the
logic address, A[7:0], always maps directly to the
translated address. The upper bits of the trans-
lated address are the unmasked values from the
mapper’s 24-bit target address value.
If the logical address does not match the mappers
target zone, then the next-highest priority mapper
examines the logical address. This process re-
peats among other mappers of the same type—i.e.
code or data—until a match is found. The lowest-
priority mapper is always guaranteed to match.
The dedicated resources on the CSI bus only de-
code 24 address lines, A[23:0]. The higher order
address lines, A[31:24] can carry diagnostics in-
formation for debugging purposes.
The mapper values are defined in the configuration
registers. In general, each mapper has
 8 bits of zone address, the value to match
against the expected logical value on A[15:8]
 5 bits for block size, specified as the log base
two of zone size in bytes
 24 bits, which form the upper bits of the CSI
physical address values. When a match occurs,
this value is placed on the CSI physical address
lines A[31:8]
 one enable bit.