Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 4
The embedded SRAM-based Configurable System
Logic (CSL) matrix provides "derivative on de-
mand" system customization. The high-
performance configurable logic architecture con-
sists of a highly interconnected matrix of CSL cells.
Resources within the matrix provide easy, seam-
less access to and from the internal system bus.
Each CSL cell performs various potential functions,
including combinatorial and sequential logic. The
combinatorial portion performs Boolean logic op-
erations, arithmetic functions, and memory. The
sequential element performs independently or in
tandem with the combinatorial function.
The abundant programmable input/output blocks
(PIOs) provide the interface between external func-
tions and the internal system bus or configurable
system logic. Each PIO offers advanced I/O op-
tions including selectable output drive current, op-
tional input hysteresis, and programmable low-
power functionality during power-down mode.
A high-performance internal system bus—called
the Configurable System Interconnect (CSI) bus—
interconnects the microcontroller, its peripherals,
and the CSL matrix. The bus provides eight bits of
read data, eight bits of write data, and a 32-bit ad-
dress. Address mapping logic translates the
8032's 16-bit address to the 32-bit address used
by the internal system bus.
Multiple masters arbitrate for bus access. Poten-
tial bus masters include the 8032 "Turbo" micro-
controller, the JTAG interface, the read and write
channels of each DMA channel, and the memory
interface unit (MIU) in some modes of operation.
Functions implemented in the CSL matrix can use
a DMA channel as a "proxy" master, re-using the
control logic already contained in the DMA chan-
nels to become a master on the CSI bus.
A memory interface unit (MIU) connects the Zy-
logic ZE5 configurable system-on-chip to external
memory. The MIU typically connects to an exter-
nal FLASH-memory device that holds the ZE5's
initialization program plus the user's code. The
MIU interface is reusable for connections to other
external components. The external read, write
control, and chip-select signals are programmable
providing flexible set-up, strobe, and hold timing.
The two-channel DMA controller provides high-
bandwidth communication between functions, up
to 40 Mbytes per second. Its easy-to-use hand-
shake simplifies interface and control logic. Func-
tions from within the CSL matrix can request DMA
transfers, the DMA controller providing "proxy" bus
mastering capabilities.
A large block of fast, byte-wide SRAM provides
internal storage for temporary data storage or for
code. Though typically used for data, code can be
Triscend
Configurable
System-on-Chip
(CSoC)
TCK TMS TDI TDO
CE- OE- D[7:0] A[17:0]WE-
188
PIO
RST-
XTALIN
XTAL
PIO
PIO
PIO
PIO
PIO
VSYS
+3.3V
PIO
PIO
PIO
PIO
PIO
PIO
Up to 125 PIO pins in
208-pin PQFP package
+3.3V
16
VCC
GND
28
GND
JTAG Connector
TCK TMS TDI TDO
Flash ROM
256Kx8
CE- WE- OE- D[7:0] A[17:0]
SLAVE-
+3.3V
VCC
GND
GND
+3.3V
GND
Figure 3. A complete Zylogic ZE520 Configurable System-on-Chip (CSoC) design.