Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
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RPW[2:0] specifies the pulse width of OE- during a
memory read sequence. The actual pulse width is
(RPW[2:0] + ½) * (system clock period). These
three bits are set to all ones by a power-on reset or
other device-wide reset, defaulting to the slowest
setting.
Table 19. Read Pulse-Width Time.
RPW2 RPW1 RPW0
Bus Clock
Cycles
0 0 0 0.5
0 0 1 1.5
0 1 0 2.5
0 1 1 3.5
1 0 0 4.5
1 0 1 5.5
1 1 0 6.5
1 1 1
7.5
(default)
XMSU enables an additional clock cycle for setup
in expansion cycles. This bit is cleared by a
power-on reset or other device-wide reset.
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This register provides control over serial-mode
initialization and over device programming for an
external, FLASH- or EEPROM-based, sequential-
access serial PROM.
CE-
SER_EN-
RESET_
OE-
76543210
CLKSDOUT
SDOUT_
EN-
CLKDIVSDIN
Mnemonic: MIUSCTL Address: FE33 h
RESET_OE- drives the RESET/OE- enable pin of
the external serial memory via the MIU's OE- pin.
This bit is set by a power-on reset or other device-
wide reset.
SER_EN- drives the write-enable input of an ex-
ternal FLASH- or EEPROM-based serial PROM for
programming. This bit is set by a power-on reset
or other device-wide reset.
CE- drives the chip-enable input of the external
serial PROM. This bit is set by a power-on reset or
other device-wide reset.
SDOUT is the external serial memory data. Only
used when programming an in-system program-
mable, external, serial PROM. Unaffected by a
reset.
SDOUT_EN- is the external serial memory write
data output enable. In serial write mode, this bit
provides direct control over the three-state enable
line of the output data buffers. Cleared by a
power-on reset or other device-wide reset.
CLKDIV controls the speed of the serial clock in
serial read mode only. When cleared, SCLK =
BUSCLK/4. When set, SCLK=BUSCLK/64. This
bit is set by default by a power-on reset or other
device-wide reset. The default is the slower mode.
SDIN is the serial memory read data. This bit is
read-only.
Address Mappers
The address mappers translate the 8032 micro-
controller’s accesses to data, program or SFR ad-
dress spaces into addresses for the Zylogic CSI
bus. Because of its architecture, an 8032 micro-
controller supports multiple address spaces, as
shown in Figure 34.
The 8032 microcontrollers has two separate, ex-
ternal 64K bytes address spaces: program and
data. Program memory holds instructions and ar-
guments used during code fetching while data
memory stores variables and other data for appli-
cations.
The shaded blocks Figure 34—external program
memory, external data memory and user-selected
SFR registers—can be directed onto the Zylogic
ZE5’s CSI bus. The MCU’s indirect and direct in-
ternal RAM spaces can not be mapped outside the
8032 microcontroller. The internally implemented
SFRs—ACC, B register, power, timers, serial
channel control, etc.—are not mapped outside the
8032 MCU to avoid software incompatibilities.
Address mappers translate the microcontroller’s 8-
or 16-bit logical address to a 32-bit physical ad-
dress on the CSI bus. Each mapper monitors mi-
crocontroller accesses to a particular type of ad-
dress space such as program, data or external
SFR address space.