Specifications

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SER_WR is used to program a FLASH- or
EEPROM-based external serial sequential-access
PROM. Cleared by a power-on reset or other de-
vice-wide reset.
DMA_RD is a reserved MIU mode used during
manufacturing. Leave this bit cleared. Cleared by
a power-on reset or other device-wide reset.
DMA_WR is a reserved MIU mode used during
manufacturing. Leave this bit cleared. Cleared by
a power-on reset or other device-wide reset.
NOTE:
The MIU control registers are part of the
ZE5’s “hidden” control register set. The
BLOCKSIZE bit in the DMAP3_CTL
register must be set in order to access the
MIU control registers. The MIU regis-
ters are normally not modified by user
application code.
M
M
I
I
U
U
T
T
i
i
m
m
i
i
n
n
g
g
C
C
o
o
n
n
t
t
r
r
o
o
l
l
R
R
e
e
g
g
i
i
s
s
t
t
e
e
r
r
s
s
The MIU timing control register defines the timing
of read and write control strobes issued by the MIU.
The write hold time value WHT[2:0] field spans the
two control bytes.
WSU2 WSU1 WSU0
76543210
WPW0WPW1WPW2WHT0WHT1
Mnemonic: MIUCTRL0 Address: FE31h
WSU[2:0] specifies the WE- setup time during a
memory write cycle. It specifies the additional
number of clock cycles added to the minimum
setup time of ½ clock when generating a memory
write cycle. The actual setup width is (WSU[2:0] +
½) * (system clock period). These three bits are
set to all ones by a power-on reset or other device-
wide reset, defaulting to the slowest setting.
Table 15. Write Setup Time.
WSU2 WSU1 WSU0
Bus Clock
Cycles
0 0 0 0.5
0 0 1 1.5
0 1 0 2.5
0 1 1 3.5
1 0 0 4.5
1 0 1 5.5
1 1 0 6.5
1 1 1
7.5
(default)
WPW[2:0] specifies the pulse width of WE- during
a memory write sequence. The actual pulse width
is (WPW[2:0] + ½) * (system clock period). These
three bits are set to all ones by a power-on reset or
other device-wide reset, defaulting to the slowest
setting.
Table 16. Write Pulse-Width Time.
WPW2 WPW1 WPW0
Bus Clock
Cycles
0 0 0 0.5
0 0 1 1.5
0 1 0 2.5
0 1 1 3.5
1 0 0 4.5
1 0 1 5.5
1 1 0 6.5
1 1 1
7.5
(default)
WHT[2:0] field specifies the width of the hold por-
tion of a write cycle. The actual hold width is
WHT[2:0] * (system clock period). These three bits
are set to all ones by a power-on reset or other
device-wide reset, defaulting to the slowest setting.
NOTE: The WHT2 bit is part of the MIUCTRL1
byte.
Table 17. Write Hold Time.
WHT2 WHT1 WHT0
Bus Clock
Cycles
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1
7
(default)
RSU1 RSU0 WHT2
76543210
RSU2RPW0RPW1RPW2XMSU
Mnemonic: MIUCTRL1 Address: FE32h
RSU[2:0] specifies the additional number of clock
cycles to add to the minimum setup time of a read
cycle. The actual setup width is (RSU[2:0] + ½) *
(bus clock period). These three bits are set to all
ones by a power-on reset or other device-wide
reset, defaulting to the slowest setting.
Table 18. Read Setup Time.
RSU2 RSU1 RSU0
Bus Clock
Cycles
0 0 0 0.5
0 0 1 1.5
0 1 0 2.5
0 1 1 3.5
1 0 0 4.5
1 0 1 5.5
1 1 0 6.5
1 1 1
7.5
(default)