Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
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BUSCLK
CE-
OE-
WE-
D[7:0] VALID VALID
SETUP STROBE
Figure 33. One-cycle write operation
using MIU.
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Generally, a wait signal is generated for every ex-
ternal memory read access, except for a read from
a fast external memory, with access time within
one clock cycle.
Memory writes operate differently. Because write
data and addresses are held in buffers, the MIU
does not need to stall the CSI bus. A wait is gen-
erated only if another memory access is requested
while the previous write is in progress.
Wait-states are also generated when the 8032 mi-
crocontroller directly accesses external memory,
bypassing the internal bus. These wait-states oc-
cur because every bypass transaction is replicated
on the internal bus for debugging purposes. The
wait signal is synchronized correctly with the repli-
cated transaction on the bus.
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Three potential sources use the MIU as an internal
system slave.
1. Any master can access the MIU via the CSI
bus.
2. The microcontroller can bypass the CSI bus
and directly access the MIU.
3. The programmable address selectors can
generate external memory requests.
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“Soft” modules implemented in the Configurable
System Logic (CSL) matrix can borrow MIU re-
sources to access external devices. Functions in
the CSL matrix can re-use the MIU's address and
data signals plus some control via the OE- and
WE- pins. The CSL matrix can request a memory
cycle by using a special mode of a Selector to gen-
erate the chip enable (CE-) to the external device.
The WE-, OE-, address and data signals are gen-
erated through the MIU. The OE- and WE- signals
behave similar to the general case. Their leading
edges are generated of the falling edge of the
clock, and their trailing edges are generated of the
rising edge of the clock. Therefore, one cycle
reads or writes are possible. Using the
WAITNEXT signal, the MIU knows if it has to ex-
tend the external command (OE- or WE-) or if it
should end the current cycle and generate a new
one.
For write cycles, the setup time is always ½ clock.
However, to improve margin at high clock rate, the
setup time can be extended by one full clock cycle.
The hold time however is only guaranteed by the
delay on the address and data lines, requiring ex-
ternal memory with 0ns hold time requirements. If
different timing is required by the application, then
the OE- and WE- signals can be generated from
within the CSL matrix. These signals would then
connect to external memory via a PIO pin.
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After a power-on reset or other device-wide reset,
the MIU begins operation as a master on the CSI
bus. The MIU is then ready to receive commands
via the external memory bus. This is useful for
slave-mode initialization. If the SLAVE- pin is held
High, then the MIU becomes a CSI bus slave dur-
ing the initialization process.
During a power-on reset or other device-wide reset,
the CE- signal is held High via an internal pull-up
to prevent spurious writes.
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The MIU and its different modes are programmed
through 4 bytes of registers.
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The MIU configuration register defines the current
operating mode of the MIU.
SER_RD
MASTER SLAVE
76543210
SER_WRDMA_RDDMA_WR
Reserved
Mnemonic: MIUMODE Address: FE30h
SLAVE, when set, indicates that the MIU is a slave
on the CSI bus. For most stand-alone applications,
this is the mode used after configuration. Cleared
by a Power-On or System Reset event.
MASTER, when set, indicates that the MIU is a
master on the internal system bus. This is the ini-
tial state of the MIU upon power-up. Set by a
Power-On or System Reset event.
SER_RD, when set, indicates that the MIU is con-
figured to read configuration data from an external
serial sequential-access PROM. Cleared by a
power-on reset or other device-wide reset.