Specifications

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The main features of the memory interface unit are:
 Support for a standard 256Kx8 external mem-
ory interface
 Support for expansion up to 4Gx8 of external
memory through PIOs
 Programmable read and write timing control
 Bypass mode to support direct access by the
8032 core
 External serial memory support
 Multi-chip expansion capabilities
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The MIU provides the interface between the inter-
nal CSI bus and external memory. The MIU moni-
tors the internal bus to determine when external
memory is accessed. During an external access,
the MIU controls external memory and generates
the appropriate read, write, and enable strobe sig-
nals.
The MIU interface timing is programmable. Three
bits define the timing of each portion of external
cycles. Read cycles are split into two sections, a
setup and an active portion, as shown in Figure 30.
In order to support one cycle reads, the minimum
setup and width values are respectively 0 and 1.
The leading edge of OE- is generated off the falling
edge of the clock. The trailing edge of OE- is gen-
erated from the rising edge of the clock. In a one
cycle read, depending on the clock duty cycle, the
setup and width of OE- are roughly half a clock
cycle each. Extra clock cycles can be added to
either the setup or the strobe width. The minimum
setup is ½ clocks and it can be extended to 7½
clocks. Similarly, the pulse width of OE- can take
a minimum of ½ clocks up to 7½ clocks. To sum-
marize, a read cycle is programmable to between
25 ns and 375 ns with a granularity of 25 ns, using
a 40 MHz system clock.
Write cycles are partitioned into three sections: a
setup, a write pulse and a hold portion, as shown
in Figure 32. The hold portion is optional. The
setup and width are similar to the read case de-
scribed above. Extra hold cycles can be added
after the trailing edge of the WE- signal to guaran-
tee various hold conditions. The fastest write ac-
cess is performed in one clock cycle, with ½ clock
for setup and ½ clock for write-pulse width. Addi-
tional clock cycles can be added to any portion of
the write cycle through the MIU configuration regis-
ter. Setup and pulse width can vary from ½ clock
to 7 ½ clocks. The hold portion varies from zero to
7 clocks. To summarize, a write cycle is pro-
grammable to between 25 ns and 550 ns with a
granularity of 25 ns, using a 40MHz bus clock.
The following timing diagrams illustrate the options
described earlier.
BUSCLK
CE-
OE-
WE-
SETUP
ACTIVE PART
OF CYCLE
Figure 30. Generalized read cycle using MIU.
BUSCLK
CE-
OE-
WE-
SETUP
ACTIVE PART
OF CYCLE
Figure 31. One-cycle read operation using MIU.
BUSCLK
CE-
OE-
WE-
SETUP STROBE HOLD
D[7:0] VALID
Figure 32. Generalized write cycle using MIU.