Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 34
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Embedded logic attached to the PIOs contains test
structures compatible with IEEE Standard 1149.1
for boundary-scan testing, permitting easy chip
and board-level testing.
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Before configuration, all PIO pins function via the
JTAG interface but with the following default condi-
tions:
 The input hysteresis is turned on
 The output drive is lowest output current mode
 The BusMinder is a pull-up resistor
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All unused but configured PIO blocks are pro-
grammed as inputs with the soft BusMinder’s pull-
up resistor enabled. This prevents unused PIO
pins from floating.
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Each PIO has built-in ESD protection capable of
protecting against a minimum discharge of 2,000
volts, using the human body model.
Memory Interface Unit
The Memory Interface Unit (MIU) provides a flexi-
ble, glueless interface between the ZE5 configur-
able system-on-chip and external memory, as
shown in Figure 29. The MIU primarily provides
access to an external memory device—typically a
256Kx8 Flash PROM—which contains the ZE5's
initialization data and the user's program code.
Other types of memory, such as static RAM or
EPROM, can substitute for the Flash PROM be-
cause the control signals are identical.
The MIU serves two purposes. First, it replaces
the original 8032's multiplexed address and data
ports that consumed the 8032's port 0 and port 2.
Instead, the MIU provides a more flexible demulti-
plexed address and data bus. Second, it provides
a convenient port for accessing external functions
from other peripheral functions, including the Con-
figurable System Logic (CSL) matrix.
As shown in Figure 29, the MIU provides a direct
connection between the 8032 microcontroller and
the external memory. By bypassing the internal
CSI bus, the Zylogic ZE5 maintains timing com-
patibility with the original 8032 implementation.
The external memory timing is variable allowing
the ZE5 to optimize or slow down accesses to fit
the particular AC characteristics of different mem-
ory devices. The MIU can also interface with an
external serial sequential-access PROM memory,
similar to those used to configure SRAM-based
field-programmable gate arrays.
The address, data, and control pins of the MIU are
also controllable from other peripheral functions,
including the Configurable System Logic (CSL)
matrix, allowing access to external peripherals or
memory devices. The MIU requires minimal hand-
shaking logic from within the CSL matrix.
Data Write
8032
"Turbo"
Microcontroller
Address
Data Read
Memory
Interface
Unit
(MIU)
Other
Peripheral
Functions
Bypass
A[17:0]
D[7:0]
CE-
WE-
OE-
External
Memory
(FLASH)
CSI Bus
Figure 29. The Memory Interface Unit (MIU) provides a glueless interface between the microcon-
troller, its peripheral functions, and external memory.