Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 32
First, the ZE5 has a dedicated external memory
interface, separate from the programmable I/O
ports. Furthermore, there are no shared PIO pins,
unless so specified in the users design. Conse-
quently, an ZE5 design may have as many as 315
PIO pins, depending on the device and package
offering. The user determines the number of ports
addressable by the processor.
Process and design technologies have advanced
significantly since the introduction of the original
8032. Consequently, the Zylogic configurable sys-
tem-on-chip family offers advanced I/O capabilities
not found in the original 8032. These features in-
clude, power-down operation, selectable drive
strength, optional input hysteresis, programmable
three-state operation, and low-voltage operation.
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The PIOs on the Zylogic ZE5 are fully 5-volt toler-
ant even though the I/O supply voltage is 3.3 volts.
This allows 5 volt signals to connect directly to the
ZE5 inputs without damage, as shown in Figure 28.
In addition, the 3.3-volt VCC can be applied before
or after 5 volt signals are applied to the I/Os. This
makes the ZE5 immune to power supply sequenc-
ing problems.
The ZE5 CSoC device accepts either TTL or
CMOS inputs from a 5-volt device. Built-in over-
voltage protection prevents any latch up or poten-
tial device damage caused by applying a 5-volt
signal to a 3.3-volt device.
Likewise, the ZE5 device outputs drive valid TTL
levels for a 5-volt device. The majority of 5-volt
devices, including 5-volt CMOS parts, have TTL-
compatible inputs.
The only potential voltage-standard mismatch oc-
curs when the ZE5 drives a pure 5-volt CMOS de-
vice with CMOS-only inputs. However, CMOS de-
vices with CMOS-only inputs are typically used for
lower power applications. Switching to a 3.3-volt
CMOS device cuts power consumption nearly in
half and eliminates any potential voltage-standard
mismatch.
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There are three storage elements in each PIO:
1. An input flip-flop/latch
2. An output flip-flop
3. An output-enable flip-flop
The functionality of each storage element is de-
fined in Table 13. Note that only the input register
can be used as a latch. Each is a 'D'-type element
and all share a common clock-enable and clock
control input. An individual flip-flop is either per-
manently enabled or selectively enabled using the
common clock-enable input.
Table 13. Flip-Flop/Input Latch Operation
(no optional inversions).
Mode D ClkEna Clock Q
During initialization
INITV
Value
D 1*

D
Flip-flop
X X 0 Q
X 1* 1 Q
Input Latch
D 1* 0 D
Both X 0 X Q
X = don’t care
1* = logic High (default value)
= rising clock edge (no clock inversions)
INITV = preloaded initialization value defined in
user’s design
The polarity of the common clock signal is individ-
ual controlled for each flip-flop within a PIO.
A user-defined initial value of a register is loaded
during the configuration process.
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Input signals flow into the device through two pos-
sible paths. The input path is a direct logical input
while the other is a registered input programmed
as either an edge-triggered flip-flop or a level-
sensitive latch.
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Each PIO input has optional input hysteresis.
When enabled, there is about ±150mV of hystere-
sis, centered around the input switching voltage,
based on the I/O supply voltage (VIO).
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QA is the registered input. Unlike the other stor-
age elements, the input register can be configured
either as an edge-triggered flip-flop or as a level-
sensitive latch as shown in Table 13.
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The data input to the input register can optionally
be delayed by several nanoseconds. With the de-
lay enabled, the setup time of the input flip-flop is
increased to negate the clock distribution delay.
This guarantees that the input register hold time is
always zero or negative, never a positive hold time.
A positive hold time requirement could lead to un-
reliable, temperature- or processing-dependent
operation.
The delay guarantees a zero hold time with re-
spect to the clock provides by the bus clock buffer.