Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
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As a single-port RAM, a CSL cell provides
 Four address inputs for a 16x1 RAM block, five
address inputs for a 32x1 block.
 A data input
 An active-High write enable input
 An invertible write clock input
The initial contents of the RAM can be pre-defined
and loaded at power-up during initialization. All
write operations are synchronized to the clock in-
put, simplifying the timing relationship of the data,
address, and write-enable signal. Also, there are
no hold time requirements for any of the RAM in-
puts after the active clock edge.
Read operations are asynchronous and depend
only on the address inputs.
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In dual-port RAM mode, two CSL cells provide true
dual-port capabilities, supporting simultaneous
read and write operations from both ports. As a
dual-port RAM, two CSL cells offer
 Two, four-input address input ports
 Two data input ports
 Two active-High write enable input ports
 A single shared, invertible write clock input
 A daisy-chained error monitor that detects si-
multaneous write operations to the same ad-
dress with different data
The initial contents of the RAM can be pre-defined
and loaded at power-up during initialization. All
write operations are synchronized to the clock in-
put, simplifying the timing relationship of the data,
address, and write-enable signal. Also, there are
no hold time requirements for any of the RAM in-
puts after the active clock edge.
Read operations are asynchronous and depend
only on the address inputs.
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The ROM function is available in two versions; a
16-deep by 1-bit wide ROM (ROM16X1) and a 32-
deep by 1-bit ROM (ROM32X1)
A 16-deep ROM provides four address lines to
address the 16 memory locations. Likewise, a 32-
deep ROM provides five address lines. The value
on the address lines directly affects the output
value.
A 16x1 ROM consumes a single CSL cell while a
32x1 requires two CSL cells operating in tandem.
The ROM's initial contents are specified in the
user's design, loaded during initialization, and can-
not be changed during operation.
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Another operating mode offered by a CSL cell is
an 8-bit, serial-in/serial-out shift register. Serial
data arrives on the SDI input. When Low, the
shift/load signal, SH, loads data on DI into the shift
register location specified by the address lines,
A[2:0]. All other shifting halts.
When SH is High, the SDI data is shifted in the first
register location. Likewise, all subsequent register
values are shifted one position toward the most-
significant location (Location 7). The value in loca-
tion 7 appears on the SDO output. The address
lines, A[2:0] select the register location presented
on the asynchronous output, O.
The enable signal, EN, disables all shifting and
loading operations when Low.
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Each CSL cell contains a ‘D’-type flip-flop. The
flip-flop provides the following controls
 An optional active-High clock enable input
 An invertible, edge-triggered clock input
 An optional asynchronous input to preload the
flip-flop to set or clear the flip-flop, defined in
the user’s design.
During the initialization process, each flip-flop is
loaded with a ‘1’ or ‘0’ as defined in the design.
This value is protected against potential spurious
writes until the end of the initialization process.
Table 12. Sequential Functionality.
D EN CK ASYNC Q
During
initialization
INITV
X X X 1 ASYNCV
X0 X 0* Q
D1*

0* D
INITV = Initial value, loaded during initialization,
defined in user's design.
ASYNCV = Asynchronous preload value, defined
in user's design.
0* = Active Low, default value if left unconnected
1* = Active High, default value if left unconnected