Specifications

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In memory mode, a CSL cell performs various
memory functions, including single- and dual-
ported RAM, read-only memory (ROM), and an 8-
bit serial-in/serial-out shift register. The small
amount of RAM inside each CSL cell is ideal for
building small register files and FIFOs. Should
larger quantities of RAM be required, the ZE5’s
large system RAM block provides fast and efficient
storage.
Table 11. Memory functions implemented in a CSL cell.
Class Function
CSL
Cells Application
RAM16x1
16x1
RAM
A3
A2
A1
A0
DI
WE
CK
1
A 16-deep by one-bit wide, clocked write, ran-
dom-access memory (RAM).
RAM32x1
32x1
RAM
A4
A3
A2
A1
A0
DI
WE
CK
2
A 32-deep by one-bit wide, clocked write, ran-
dom-access memory (RAM).
RAMDUAL
16x1
Dual-Port
RAM
CK
A3
A2
A1
A0
DA
WEA
WEB
B3
B2
B1
B0
DB
Contention
Detection
2
A 16-deep by one-bit wide, clocked write,
dual-port RAM supporting simultaneous read
and write operations from both ports. Also
includes write contention circuitry to detect
simultaneous write operations to the same
location with different data.
ROM16x1
16x1
ROM
A3
A2
A1
A0
1
A 16-deep by one-bit wide read-only memory
(ROM).
ROM32x1
32x1
ROM
A4
A3
A2
A1
A0
2
A 32-deep by one-bit wide read-only memory
(ROM).
Memory
SHIFT8
EN
A2
A1
A0
DI
SH
CK
SDI
SDO
1
An 8-bit serial-in/serial-out shift register with
selectable output tap and shift/load control.