Specifications

25 www.zylogic.com.cn
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The general-purpose interconnect, shown in
Figure 22, distributes signals within a CSL bank.
Metal lines of various lengths and purposes con-
nect to individual CSL cells, to the horizontal and
vertical breakers, and to the distributed array of
routing matrices. Each routing matrix provides
connections between the various lines entering or
exiting the segment. The various interconnect re-
sources are described below.
 8 Short Segment lines in each vertical and
horizontal channel.
 8 Long Lines in each vertical and horizontal
channel. These long lines traverse the width or
breadth of the CSL bank. The vertical long
lines optionally distribute the outputs from the
Selectors located in the vertical breaker. The
horizontal long lines optionally distribute ad-
dress signals from CSI bus.
 Bus clock and 3 of 6 global buffer signal
lines in every vertical channel. The bus clock
signal is distributed globally to all resources on
an ZE5 CSoC device. Within a CSL bank, any
three of the six global buffer signals are avail-
able.
BBUF0BCLK
BBUF1
BBUF2
BBUF3
GBUF0
GBUF1
GBUF2
GBUF3
GBUF4
GBUF5
Figure 24. The bus clock signal and any 3 of
the 6 global buffer signals are avail-
able within a CSL bank.
 A carry/cascade signal between adjacent
pairs of CSL cells, for faster arithmetic functions
and for wide logic functions.
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Beyond the general-purpose signals, the pro-
grammable interconnect also distributed data
signals to and from the CSI bus.
 CSI Write Data is accessible at every routing
matrix, distributed throughout the CSL bank.

4 Multiplexer Chains for distributing bidirec-
tional data across a CSL bank. The multiplexer
chains behave much like a bidirectional, three-
state bus but avoids the potential data-
contention problems and associated power
consumption of a three-state bus because all
signals are unidirectional.
 CSI Read Data paths gather the values of indi-
vidual data lines from throughout the device.
Ultimately, all the signal return to the CSI bus.
The signals from individual bit lines are gath-
ered via an OR-chain.
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Though the interconnect was designed to minimize
any directional signal-flow preferences, there are
few biases inspired by the architecture, as shown
in Figure 25.
Enables, Control
Carry, cascade
Clocks
Selector decodes
Data
CSI Address
Figure 25. The interconnect architecture in-
spires a few signal-flow biases.
Clock signals prefer the vertical channels, either to
take advantage of the four clock buffers available
within a CSL bank or the direct connections be-
tween the CSL cell's clock input and the vertical
long lines.
Likewise, other control signals and enable signals
prefer vertical channels. Addresses decoded us-
ing Selectors also prefer vertical channels because
vertical long lines distribute these signals from the
vertical breakers.
Wide arithmetic functions or wide logic functions
benefit from the built-in carry/wide interconnect,
which prefers a vertical orientation, from bottom to
top. Other orientations are possible, though with
decreased performance.
Individual CSI bus address signals are distributed
using the horizontal long lines and consequently
prefer horizontal channels.
The multiplexer chains, designed to distribute bidi-
rectional data, traverse a CSL bank horizontally.
As a result, data flow prefers the horizontal chan-
nels.