Specifications

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Table 6. CSL Banks by Device.
CSL Banks
Part
Number
Columns Rows Total
Total
Cells
ZE502 2 1 2 256
ZE505 2 2 4 512
ZE512 3 3 9 1,152
ZE520 4 4 16 2,048
ZE532 5 5 25 3,200
Vertical and horizontal breakers separate the indi-
vidual CSL banks on a device, as shown in Figure
20. Vertical breakers appear at the top of every
CSL bank. Horizontal breakers appear between
adjacent columns of CSL banks. The breakers
contain Configurable System Interconnect (CSI)
bus resources. The horizontal breakers distribute
CSI bus address signals to the CSL banks. The
vertical breakers distribute the Selector input and
output signals, breakpoint control signals, the
global buffer signals, and the wait-state control
signals. The CSI read data return path is also lo-
cated in the vertical breakers.
Signals from one CSL bank can cross into other
banks via the breakers, though crossing a breaker
adds delay to the signal.
Sideband signals originate and terminate in re-
sources along the top edge of the device.
B
B
a
a
n
n
k
k
R
R
e
e
s
s
o
o
u
u
r
r
c
c
e
e
s
s
Each CSL bank consists of 8 columns by 16 rows
of CSL cells, totaling 128 CSL cells per bank.
Figure 21 shows the basic layout of the cells within
a bank. Pairs of adjacent CSL cells share re-
sources to build more complex cell functions. The
address selectors, located in the vertical breaker
above the bank, distribute any decoded address.
There is one address selector per column of 16
CSL cells.
Programmable interconnect surrounds the CSL
cells. These programmable "wires" allow a signal
originating from one CSL to communicate with one
or more CSL cells, even those in other CSL banks.
Likewise, signals to and from the CSI bus are dis-
tributed to and from individual CSL cells.
CSL Bank
Selectors
Vertical
Breaker
Adjacent
CSL Cells
Figure 21. A CSL bank consists of 8 columns by 16 rows of CSL cells, a 128 in total.