Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 20
onto the Data Read output bus, part of the CSI
socket.
Bus Clock
RdSel
DATA
Data Read
[7:0]
Figure 16. A single-cycle read transaction from
a CSL “soft” module.
Figure 17 demonstrates a similar transaction, ex-
cept that the CSL “soft” module requires two clock
cycles to provide the read data. The CSL “soft”
module's selector asserts the initial wait-state.
When the selector detects that the system is ad-
dressing its target address range, it asserts its
RDSEL signal and automatically asserts an initial
wait-state.
Seeing a wait-state during the first bus cycle, the
system holds its Address values. Correspondingly,
the selector continues to assert its RDSEL output.
Because the CSL “soft” module can present data
during the second bus cycle, it does not assert its
WAITNEXT signal. The system, seeing no wait-
states during the second bus cycle, continues on
to the next transaction. Consequently, the selector
de-asserts its RDSEL output after the second bus
cycle.
Bus Clock
Waited
By
Selector
RdSel
DATA
Data Read
[7:0]
Figure 17. A two-cycle read transaction from a
CSL “soft” module.
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There are three general rules for asserting a wait-
state during a bus transaction to a CSL “soft” mod-
ule, depending on the “soft” module's response
time.
1. If the “soft” module can respond within a single
bus cycle, no wait-states are inserted.
2. If the “soft” module can responds by the sec-
ond bus cycle, the address selector is config-
ured to insert a single wait-state.
3. If three or more bus cycles are required before
the “soft” module can respond, an address se-
lector is configured to insert the initial wait-
state and the “soft” module must assert the
WAITNEXT signal to insert additional wait-
states.
Figure 18 shows an example transaction where the
selected “soft” module uses the WAITNEXT signal
to insert wait-states. During the first bus cycle, the
addressed “soft” module's selector asserts it
RDSEL output. In this example, the “soft” module
always requires at least one wait-state, so the se-
lector inserts the initial wait-state. The “soft” mod-
ule is not ready to respond in the first bus cycle, so
the “soft” module asserts WAITNEXT, causing a
wait state during the next bus cycle
During the second bus cycle, the system continues
providing address. The selector continues assert-
ing RDSEL. The “soft” module determines that it
unable to respond during this cycle and continues
asserting WAITNEXT.
Finally, during the third bus cycle, the “soft” module
is ready to respond. The “soft” module provides
data on the Read Data signals on the CSI socket.
The “soft” module also de-asserts WAITNEXT,
indicating that it is ready to supply data.
Bus Clock
RdSel
Waited
By
Selector
By CSL
WaitNext
DATA
Data Read
[7:0]
Figure 18. A multi-cycle transaction using
WAITNEXT to insert wait-states.
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All of the signals on the CSI socket interface are
designed to be processor independent. “Soft”
modules designed using this interface can be re-
used with future Zylogic configurable system-on-
chip families.
However, some signals are processor specific.
The signals are called "side-band" signals. For the
Zylogic ZE5 family, these side-band signals in-
clude 8032-specific functions.
Table 5. ZE5 Family Side-band Signals.
ZE5 Function 8032 Signal
Timer 0 external input T0