Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
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- Embedded debugging capabilities
 Embedded Configurable System Logic (CSL)
matrix
- Fast, flexible CSL logic cells support combina-
torial logic, arithmetic, memory, sequential,
and bus functions
- Up to 3,200 CSL cells per device
- Easy, synchronous access to and from the
system bus
- Programmable intercommunications network
between system bus, CSL cells, and pro-
grammable I/O (PIO) pins
- Contention-free bi-directional bussing
 High-performance, dedicated Configurable
System Interconnect (CSI) system bus
- 8-bit read and write data, 32-bit address
- Up to 40 Mbytes/sec transfer rates
- Simple, synchronous interface to CSL periph-
erals, seamless connection to the microcon-
troller
- Multi-master bus with round-robin arbitration
- Expandable to off-chip function through mem-
ory interface unit (MIU)
- Flexible on-chip address decoders provide
easy access to CSL functions
- Programmable wait-state support
- Open standard
- Forward compatible with future Zylogic con-
figurable system-on-chip devices
 Enhanced programmable input/output (PIO)
ports
- Up to 315 user-programmable I/O per device
- Inputs, outputs, or bi-directional ports for the
microcontroller, dedicated peripherals, or pro-
grammable logic peripherals
- Selectable output drive from 4 mA to 12 mA
- BusMinder™ circuit provides pull-up, pull-
down, or weak-follower capability
- Optional input hysteresis
- Optional power-down operation, individually
selectable on every pin
- Input, output and output enable flip-flops for
optimal set-up and clock-to-output perform-
ance
- 5 volt tolerant inputs while operating at 3.3
volts
 Memory interface unit (MIU) for flexible,
glue-less interface to external memory
- Direct connect interface to an external
256Kx8 memory for initialization and code
storage
- Expandable from 18 up to 32 address lines
- Variable-speed read/write timing simplifies in-
terface design
- Access external peripherals by sharing MIU
data and address pins
 Two-channel advanced DMA controller
- Proxy bus masters for CSL “soft modules”
- Up to 40 Mbytes/s transfer rate (1 byte/cycle)
- Auto-initialization of channels
-
Multiple addressing modes
- Software-initiated DMA requests
- Optional interrupt at end of a transfer
- Block data transfers
- CRC checking
- DMA channel request and acknowledge sig-
nals distributed to the CSL matrix
 Programmable power-down modes
- Selectively disable function during power-
down
- Typically consumes less that 50 µA in full
power-down mode
 On-chip oscillator, crystal oscillator ampli-
fier, and clock distribution circuitry
Table 1. Zylogic ZE5 Configurable System-on-Chip Family
Device
Embedded
Processor
Core
Dedicated
Resources
System
RAM
Configurable
System
Logic (CSL)
Cells
CSI
Address
Selectors
PIO*
Pins
(Max)
ZE502 8Kx8 256 16 92
ZE505 16Kx8 512 32 124
ZE512 32Kx8 1,152 72 188
ZE520 40Kx8 2,048 128 252
ZE532
8032 "Turbo"
(3) 16-bit counters
USART
Watchdog timer
Interrupt controller
High-speed internal bus
Memory interface unit
2-channel DMA controller
Power management
Power-on reset
Hardware breakpoint unit
JTAG port
64Kx8 3,200 200 316
* Maximum PIO on each base device, actual PIO count depends on package style and initialization mode. See Table 45.