Specifications

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trix may require wait-states, either because the
“soft” module handshakes with another asynchro-
nous device or if the “soft” module is too slow to
respond in a single bus cycle.
If a “soft” module requires any wait-states, a selec-
tor must assert the first wait-state. The selector
will only assert a wait-state if the system is access-
ing the selector's target address space.
Should a “soft” module require additional wait-
states beyond the initial wait-state asserted by the
selector, then the “soft” module indicates additional
wait-states by asserting the WAITNEXT signal on
the CSI socket interface.
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The CSI socket interface includes signals to moni-
tor and control hardware breakpoint events. These
signals can be used to aid system-level debugging.
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CSL functions can force a hardware breakpoint
event by asserting the BREAK signal. The hard-
ware breakpoint unit typically only monitors trans-
actions on the CSI bus. The BREAK signal allows
CSL functions to interact with the hardware break-
point unit.
For example, a CSL function could be monitoring a
serial communications stream that rarely interacts
with the system bus. Upon detecting a particular
pattern, the CSL function could force a breakpoint
event, stopping the system. The state of the sys-
tem or CSL functions could then be monitored
through the JTAG port.
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CSL functions can monitor hardware breakpoint
events using the EVENT signal. When EVENT is
asserted, a hardware breakpoint event has oc-
curred, either caused by the hardware breakpoint
event or by another function in the CSL matrix.
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The following section describes example CSI bus
transactions, demonstrating the interaction of a
CSL “soft” module and the CSI bus socket.
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During a data write transaction, the system sends
data to a CSL “soft” module. The system presents
both write data and address.
Figure 14 shows a single-cycle write transaction to
a CSL “soft” module. Write data and address are
presented on the CSI socket interface. The ad-
dress is decoded using one the selector functions.
If the transaction is to the address selector's tar-
geted address range, then the selector asserts its
WRSEL signal. The CSL “soft” module uses
WRSEL to enable a register and capture the write
data.
Bus Clock
WrSel
Data Write
[7:0]
DATA
Figure 14. A single-cycle write transaction to a
CSL “soft” module.
Figure 15 demonstrates a similar transaction, ex-
cept that the CSL “soft” module requires two clock
cycles to capture the write data. The CSL “soft”
module's selector is configured to assert the initial
wait-state. When the selector detects that the sys-
tem is addressing its target address range, it as-
serts its WRSEL signal and automatically asserts
an initial wait-state.
Seeing a wait-state during the first bus cycle, the
system holds its Data Write and Address values.
Correspondingly, the selector continues to assert
its WRSEL output. Because the CSL “soft” module
will capture the write data during the second bus
cycle, the “soft” module does not assert its
WAITNEXT signal to insert additional wait-states.
The system, seeing no wait-states during the sec-
ond bus cycle, continues on to the next bus trans-
action. Consequently, the selector de-asserts its
WRSEL output after the second bus cycle.
Bus Clock
Waited
By
Selector
WrSel
DATA
Data Write
[7:0]
Figure 15. A two-cycle write transaction to a
CSL “soft” module.
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During a data read transaction, the system re-
ceives data from a CSL “soft” module. The system
presents both the read address and waits for the
read data.
Figure 16 shows a single-cycle read transaction
from a CSL “soft” module. The read address is
presented on the CSI socket interface. The ad-
dress is decoded using one the selector functions.
If the transaction is to its targeted address range,
then the selector asserts its RDSEL signal. The
CSL “soft” module uses RDSEL to enable data