Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 18
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A selector provides a relocatable control register
for CSL “soft” modules requiring DMA access. The
DMA control register enables requests and steers
the request and acknowledge signals to the se-
lected DMA channel. DMA control register. See
the "DMA Controller" section for more information.
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A “soft” module can access an external device us-
ing PIO pins or by re-using the pins on the memory
interface unit (MIU). A special selector mode al-
lows a CSL function to access and handle a trans-
action through the MIU, as shown in Figure 13.
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The CSI socket interface includes signals to moni-
tor and control wait-states on the internal system
bus.
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The WAITED signal indicates that a wait-state was
asserted during the previous bus cycle. This sig-
nal is typically used in control logic for functions
such as FIFOs and dual-port memory.
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Some CSL “soft” modules require wait-states if the
they are too slow to respond in a single bus cycle.
If any wait-states are required, the initial wait-state
must be asserted using an address selector.
If a “soft” module requires more than one wait-
state, it must assert the WAITNEXT signal before
the next rising clock edge on Bus Clock. When
asserted, the WAITNEXT signal causes a wait-
state on the next bus cycle.
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Some “soft” modules implemented in the CSL ma-
Match0: Addr. Bit = Low
Match1: Addr. Bit = High
A31
A0 A1 A2
CSI Bus Address
READ
BCLK
RDSEL
SEL
WRITE
Figure 12. In chip select mode, an address selector decodes any read or write transaction to the
target address range.
A[17:0]
D[7:0]
OE-
WE-
CE-
Triscend
E5
CSoC
A[17:0]
Flash
D[7:0]
OE-
WE-
CE-
A[n:0]
Additional
Device
D[7:0]
OE-
WE-
CE-
CSL_CE-
Figure 13. Other external devices share the ZE5's Memory Interface Unit (MIU) signals. The chip
enable for the Flash connects directly to the ZE5's CE- pin. All other devices use a separate Chip
Select function, located in the CSL matrix.