Specifications

17 www.zylogic.com.cn
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The MATCH0 and MATCH1 register values are
automatically defined by the Zylogic FastChip de-
velopment system at design time. These register
values are not changed by application software.
The addresses loaded into MATCH0 and MATCH1
are symbolically defined by the user during hard-
ware design. The user specifies
 The symbolic name for the address range.
This is the name used in application software to
refer to the target address range.
 The size of the addressed range, which must
be a power of two, ranging from ‘1’ indicating a
single byte to ‘16M’ indicating a 16M byte re-
gion.
 The address space or spaces to which the se-
lector should respond. In conjunction with the
address mapper, a selector detects transac-
tions to a specific address space. The ZE5,
based on a standard 8032 microcontroller, sup-
ports the following address spaces.
 DATA, which corresponds to the 8032's
XDATA memory space
 SFR (Special Function Register), which is
a 128-byte region unique to the 8032 ar-
chitecture.
The Zylogic FastChip development system exam-
ines these settings from all of the address selec-
tors defined in the hardware design. It then allo-
cates physical addresses to each selector. The
corresponding 8032 logical addresses are defined
and specified in a header file, used with the user’s
application code.
The MATCH0 and MATCH1 values, defined by the
Zylogic FastChip development system, are loaded
into the selectors during the initialization process.
FastChip also defines the values initially loaded
into the address mapper registers.
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An address selector performs one of three poten-
tial functions as shown in Table 4.
Table 4. Address Selector Types.
Select
Modes Ports Function
RDSEL Read decode
Selector
WRSEL Write decode
RDSEL R/W- control
Chip Select
SEL Chip select
REQSEL DMA request
DMA Control
ACKSEL DMA acknowledge
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A selector separately decodes read and write op-
erations to the target address range, as shown in
Figure 11. The RDSEL output indicates a read
operation, the WRSEL output indicates a write op-
eration.
A selector function is called SELECT in the design
library.
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A selector in the chip select mode decodes any
read or write transaction to the target address
range, read or write. Figure 12 shows a functional
drawing of a chip select function. The SEL per-
forms like a chip select function. The RDSEL out-
put is asserted only during read operations.
A selector function is called CHIPSEL in the design
library.
Match0: Addr. Bit = Low
Match1: Addr. Bit = High
A31
A0 A1 A2
CSI Bus Address
RDSEL
WRSEL
READ
WRITE
BCLK
Figure 11. The distributed address selector functions decode read and write transactions to a
target address range. The selectors eliminate the need to build decoding logic using
CSL resources.