Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 16
A
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All 32 address bits are presented via the CSI inter-
face socket. Typically, only a few, if any, of the
address signals are used by functions in the CSL
matrix. Typically, the actual decoding of the ad-
dress bus is performed using the address selector
resources.
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A
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The CSI socket interface practically eliminates the
need to use any CSL matrix resources to decode
bus transactions. One of the more important ele-
ments in the CSI socket interface is the program-
mable address decoder function, generically called
a selector. A selector performs functions much like
a chip select unit or an address decoder built in a
PAL-type device.
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S
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O
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A selector detects a transaction to a specified
range of CSI bus addresses, including the particu-
lar address space. A selector decodes the full 32-
bit address bus. If a transaction is to its target ad-
dress range, the selector asserts one of its outputs
on the same clock edge that the system provides
write data and address, synchronized to the sys-
tem clock. This approach dramatically simplifies
the logic used to access CSL “soft” modules.
The number of available selectors depends on the
particular device. The number of selectors grows
with the increasing size of the CSL matrix. There
is one selector for every sixteen CSL cells, as
shown in Table 3.
Table 3. Number of selectors by device.
Device Selectors
ZE502 16
ZE505 32
ZE512 72
ZE520 128
ZE532 200
Functionally, each selector is similar to diagram
shown in Figure 11. Each selector contains two
32-bit registers that define the target address. The
MATCH0 register defines which address bits
match when the individual bit is Low. The
MATCH1 register defines which address bits
match when the bit is High. If the same bit location
is set in both registers, then the corresponding ad-
dress bit is a "don't care."
If each address bit matches with values defined in
the MATCH0 and MATCH1 register, then the se-
lector further decodes read or write operations. If
the address matches, and there is a read transfer
to this location, then the selector asserts its
RDSEL output. Likewise, if the transfer is a write,
then the selector asserts its WRSEL output.
DMA ReqSel
Wait Next Cycle
Force Breakpoint
8
Data Read
Read Enable
32
Address
Data Write
8
Selector Decode
DMA Acknowledge
Bus Waited
Breakpoint Event
Bus Clock
CSL Logic
Function
Synchronous Interface
Figure 10. The CSI bus socket represents a simple-to-use, synchronous interface to custom logic
functions implemented in the CSL logic matrix.