Specifications

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Configurable System Interconnect (CSI) Bus
The Configurable System Interconnect (CSI) bus,
shown in Figure 9, bridges the microcontroller to its
peripherals and functions implemented in the Con-
figurable System Logic (CSL) matrix. The CSI bus
provides a processor-independent migration path
to future generations of configurable system-on-
chip devices. User-defined and library-provided
“soft” modules can be moved to future Zylogic con-
figurable system-on-chip families with little or no
modification
The CSI bus socket provides a simple, synchro-
nous interface to functions implemented in the CSL
matrix, as shown in Figure 10. The CSI bus inter-
face socket consists of the following signals.
 An 8-bit write data port
 An 8-bit read data port, including a read enable
signal to enable the read data back onto the
CSI system bus.
 A 32-bit address port.
 A set of address selector (chip select) functions.
The number of selectors varies according to
device size as shown in Table 3. The selectors
optionally steer DMA request and acknowledge
signals to and from the CSL matrix.
 The bus clock.
 Wait-state control and monitor signals.
 Hardware breakpoint control and monitor sig-
nals.
D
D
a
a
t
t
a
a
R
R
e
e
a
a
d
d
B
B
u
u
s
s
Data is presented to the 8-bit read bus when the
selected CSL logic function or "soft" module as-
serts its read enable signal. The read data values
from all functions are logically OR-ed together.
Consequently, all unselected CSL functions drive
the read bus with zeroes. Only the selected func-
tion presents ones. Read data can be presented
during every active bus cycle.
D
D
a
a
t
t
a
a
W
W
r
r
i
i
t
t
e
e
B
B
u
u
s
s
The eight data write bits are presented on the CSI
socket. Write data may be presented during every
active bus cycle.
Data Write
Data Read
Bus Clock
Breakpoint
Control
Wait-State
Control
Address
Selectors
Configurable System Logic (CSL) Matrix
8032
"Turbo"
Microcontroller
Side-band Signals
CSI Socket Interface
Configurable System Interconnect (CSI) Bus
DMA Request/
Acknowledge
2-Channel
DMA Controller
Hardware
Breakpoint Unit
Figure 9. The Configurable System Interconnect (CSI) bus and the socket interface to "soft"
modules in the CSL matrix.