Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 14
REQSEL
ENBLSEL
Configurable
System Logic
DMA Select Register
DMA0 REQ
Request to
DMA Controller
DMA1 REQ
Figure 6. A DMA Control Register steers DMA
requests to the appropriate channel.
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Once a “soft” module requests a DMA transfer,
control over the transaction shifts to the DMA
channel. The DMA channel requests the CSI bus.
Once granted, the DMA channel asserts is ac-
knowledge signal, which is steered back to the
requesting CSL “soft” module via the ACKSEL
output. The control logic is shown in Figure 7.
When ACKSEL is asserted High, the CSL module
should respond appropriately. During a DMA read
(I/O-to-memory transfer), the CSL module should
present data on the Data Read bus when ACKSEL
is asserted. During a DMA write (memory-to-I/O
transfer), the CSL module should accept the data
on the Data Write bus when ACKSEL is asserted.
BUSCLK
D
Q
ACKSEL
ENBLSEL
1
0
Configurable
System Logic
DMA Select Register
DMA1 ACK
DMA0 ACK
Acknowledge from
DMA Controller
Figure 7. DMA acknowledge signals are steered
back to the requesting CSL “soft”
module.
The requesting device must be ready to accept the
ACKSEL signal in a single cycle, since wait state
capabilities are reserved strictly for memory-
mapped operations. The DMA controller is de-
signed to maximize bus bandwidth.
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Figure 8 shows the waveform for a typical DMA
write operation, i.e., a memory-to-I/O transfer.
Prior to the first request, one of the DMA channels
is configured for a DMA write operation and the
proper values loaded into its configuration registers.
Likewise, a DMA control register—part of a CSL
“soft” module function—is enabled (ENBL=1) and
the channel select bit is set to steer signals to the
proper DMA channel (SEL=0 for channel 0, SEL=1
for channel 1).
The remainder of the transaction is as shown
Figure 8.
1. The requesting “soft” module asserts its
REQSEL DMA request signal. Within the DMA
control register, this incoming request is
steered to the proper DMA channel.
2. The DMA channel requests the CSI bus from
the bus arbiter. This process may require mul-
tiple clock cycles.
3. Once the bus arbiter grants the bus to the
DMA controller, the DMA presents the transfer
address, the write data, and asserts its ac-
knowledge signal. Within the DMA control reg-
ister, the DMA channel's acknowledge signal is
steered back to the requesting CSL “soft”
module function. Consequently, the ACKSEL
signal is asserted, signaling the “soft” module
that data is available. The “soft” module uses
the ACKSEL signal to enable a register and
capture the value presented on the Data Write
bus.
Data Write
[7:0]
AckSel
Bus Clock
ReqSel


DATA
Figure 8. Example DMA Write operation.
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“Soft” modules implemented in the CSL matrix are
bus slaves, unable to request and control the bus
by themselves. However, a CSL module can use
the dedicated DMA controller as a "proxy" bus
master.
A bus master requires interaction with the bus arbi-
ter, registers and counters to track addresses, and
state machines to handle the bus transfer protocol.
Such logic would consume CSL logic resources, if
direct bus mastering were supported. A more effi-
cient approach is to re-use the dedicated re-
sources already built into the DMA controller.
The DMA controller contains the logic to arbitrate
for the bus, track address, and control transfers. A
CSL “soft” module uses the DMA controller as a
"proxy" master, causing the DMA controller to arbi-
trate for and control the bus transaction.