Specifications

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This register is shared by both DMA channels.
Cleared by a power-on reset or other device-wide
reset.
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"Soft" modules implemented in the Configurable
System Logic matrix have full access to DMA ser-
vices. Access is provided via distributed DMA con-
trol registers that steer DMA requests from periph-
erals to the appropriate DMA channel and steer
the appropriate DMA channel acknowledge signal
back to the peripheral, as shown in Figure 5.
REQSEL
Configurable
System Logic
DMA Control Register
ACKSEL
DMA
Channel 1
Request
Acknowledge
DMA
Channel 0
Request
Acknowledge
Figure 5. DMA Control Registers steer control
signals from CSL “soft” modules to
the DMA channels.
DMA control registers share the same program-
mable address selector functions also used for
address decoding and chip selects. See Table 3
for the number of selectors available in each de-
vice.
The address for a DMA control register is pro-
grammable, similar to any function using a Selec-
tor. A symbolic address name for the specific
DMA control register is provided during design.
The actual address assignment is usually left to
the Zylogic FastChip development system. All
DMA control registers are single-byte registers and
must be located within data or SFR memory
spaces.
An individual DMA control register controls a uni-
directional DMA transfer, i.e., a memory-to-I/O
(DMA write) or an I/O-to-memory (DMA read)
transaction. However, a DMA control register is
associated with a specific DMA channel by chang-
ing the SEL bit within the control register. Two
DMA control registers are required for DMA read
and DMA write operations from the same periph-
eral.
A DMA control register is enabled for DMA access
by setting the ENBL bits. Until enabled, all DMA
requests (REQSEL) from a DMA control register
are ignored.
In standard use, only one DMA control register
should be enabled per channel, per direction at
any time, for a maximum of four. These four con-
trol registers cover individual DMA read and write
operations from both channels 0 and 1. Another
DMA control register can be enabled via software
after first disabling the active control register.
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- - SEL ENBL - - SEL ENBL
76543210
Write both nibbles with duplicate data.
Read register and OR bits from each nibble.
Mnemonic: User-Defined Address: User Defined
Undefined bit locations are reserved and return 0
when read.
NOTE:
The distributed DMA Control registers
only connect to either the high nibble or
the low nibble of the CSI data bus. Con-
sequently, application code should write
duplicate copies of the high and low nib-
ble. When reading, only the high or the
low nibble will contain valid data. The
high and low nibbles should be ORed
together to determine the actual settings.
SEL steers control signals to and from the DMA
controller. If SEL is cleared, the REQSEL input
and ACKSEL output signals are steered to DMA
channel 0. If SEL is set, then the signals are
steered to DMA channel 1. The SEL control bit
must be written to both bits 5 and 1. When read,
both bits must be ORed together.
ENBL, when set, allows the CSL “soft” module to
access the DMA controller through the REQSEL
input and ACKSEL output associated with DMA
Control register. When ENBL is cleared, the DMA
controller ignores any requests from the CSL mod-
ule and the CSL module ignores any DMA ac-
knowledges. The ENBL control bit must be written
to both bits 4 and 0. When read, both bits must be
ORed together.
A DMA control register is reset to 00h by a reset.
There is unrestricted read/write access to this reg-
ister.
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To request a DMA transfer, the CSL “soft” module
function asserts the REQSEL input on the DMA
control register, as shown in Figure 6. If enabled
(ENBL=1), the REQSEL signal is forwarded to ap-
propriate DMA channel request, depending on the
SEL value. If SEL=0, then REQSEL requests
channel 0, else REQSEL requests channel 1. If
disabled (ENBL=0), the request is blocked.