Specifications

iii
Z
YLOGIC ZE5 SWITCHING CHARACTERISTIC
GUIDELINES ...........................................................95
General ZE5 Timing Characteristics ................95
JTAG Interface Timing Characteristics ............96
Pin-to-Pin Guaranteed Timing Specifications ..96
Memory Interface Unit (MIU) Timing
Characteristics..................................................99
Asynchronous Memory Interface Timing........102
Configurable System Interconnect (CSI) Socket
Timing Guidelines...........................................103
Sideband Signal Timing Characteristics ........107
Configurable System Logic (CSL) Cell
(Combinatorial Logic Mode, Sequential Mode)
........................................................................108
Configurable System Logic (CSL) Cell
(Arithmetic Mode) ...........................................110
Configurable System Logic (CSL) Cell (Memory
Mode, Single-Port RAM) ................................111
Configurable System Logic (CSL) Cell (Memory
Mode, Dual-Port RAM) ...................................113
Configurable System Logic (CSL) Cell (Memory
Mode, 8-bit Shift Register)..............................114
Bus Clock and Global Buffers ........................115
Programmable Input/Output (PIO) Timing
Guidelines.......................................................116
O
UTPUT BUFFER SWITCHING CHARACTERISTICS ...118
O
RDERING INFORMATION......................................119
S
ALES OFFICES ...................................................119
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