Specifications

®
Z
Z
y
y
l
l
o
o
g
g
i
i
c
c
Z
Z
E
E
5
5
C
C
o
o
n
n
f
f
i
i
g
g
u
u
r
r
a
a
b
b
l
l
e
e
S
S
y
y
s
s
t
t
e
e
m
m
-
-
o
o
n
n
-
-
C
C
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h
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F
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m
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C O N T E N T S
OVERVIEW ...............................................................3
8032
"TURBO" MICROCONTROLLER .........................5
Programmable I/O Ports.....................................5
UART..................................................................5
Timers.................................................................6
Interrupts ............................................................6
Data Pointers......................................................6
Power Management ...........................................6
Power-On reset ..................................................6
DMA
CONTROLLER..................................................6
Functional Description........................................7
DMA Initialization and Termination.....................7
Transfer Modes ..................................................7
Bus Address Generation ....................................8
Data FIFO...........................................................8
CRC Feature ......................................................8
Interrupts Generation .........................................9
Configuration Registers......................................9
Interfacing CSL Peripherals to the DMA
Controller ..........................................................13
C
ONFIGURABLE SYSTEM INTERCONNECT (CSI) BUS15
Data Read Bus .................................................15
Data Write Bus .................................................15
Address Bus .....................................................16
Address Selectors ............................................16
Address Selector Operation .............................16
Address Specification.......................................17
Address Selector Modes ..................................17
Wait-State Monitor and Control Signals ...........18
Breakpoint Event Monitor and Control Signals 19
CSI Bus Transactions.......................................19
Side-band Signals ............................................20
C
ONFIGURABLE SYSTEM LOGIC (CSL)....................22
Bank Resources ...............................................23
CSL Cell Capabilities........................................26
Logic Functions ................................................26
Arithmetic Functions.........................................26
Memory Functions............................................29
Sequential Functions........................................30
P
ROGRAMMABLE INPUT/OUTPUT (PIO) PINS...........31
Creating a PIO Port for the Microcontroller......31
5-Volt Tolerant I/Os..........................................32
Storage Elements.............................................32
PIO Input Side..................................................32
PIO Output Side...............................................33
Other PIO Options............................................33
Low-Power Mode .............................................33
JTAG Support ..................................................34
Default, Unconfigured State.............................34
Default, Configured State.................................34
Electro-static Discharge (ESD) Protection.......34
M
EMORY INTERFACE UNIT......................................34
Functional Description .....................................35
Initialization of the MIU.....................................36
MIU Register Description.................................36
A
DDRESS MAPPERS...............................................38
Code mappers..................................................41
C1, C2 – Fully programmable code mappers..42
Data mappers...................................................42
SFR export mapper..........................................44
Default Values for Higher-Order Address
Mappers ...........................................................45
S
YSTEM DEBUGGER...............................................45
On-Chip Debugging Support............................45
Debugging Support System Requirements .....47
C
ONFIGURATION REGISTER UNIT (CRU).................48
S
YSTEM INITIALIZATION ..........................................48
Parallel Mode ...................................................49
Serial Initialization ............................................49
JTAG Initialization ............................................50
Slave Mode ......................................................51
'Stealth' Mode...................................................51
Size of Initialization Data..................................52
Time to Initialize an ZE5 CSoC Device............52
VSYS Control...................................................53
C
LOCKING AND GLOBAL SIGNAL DISTRIBUTION.......53
System clock select (BCLK).............................53