Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 12
Channel 0:
DMA Pending Requests Channel 0 (REQ[7:0])
REQ7 REQ6 REQ5 REQ4 REQ3 REQ2 REQ1 REQ0
76543210
Mnemonic: DMAPREQ0_0 Address: FF32h
DMA Pending Requests Channel 0 (REQ[15:8])
REQ15 REQ14 REQ13 REQ12 REQ11 REQ10 REQ9 REQ8
76543210
Mnemonic: DMAPREQ0_1 Address: FF33h
Channel 1:
DMA Pending Requests Channel 1 (REQ[7:0])
REQ7 REQ6 REQ5 REQ4 REQ3 REQ2 REQ1 REQ0
76543210
Mnemonic: DMAPREQ1_0 Address: FF46h
DMA Pending Requests Channel 1 (REQ[15:8])
REQ15 REQ14 REQ13 REQ12 REQ11 REQ10 REQ9 REQ8
76543210
Mnemonic: DMAPREQ1_1 Address: FF47h
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The DMA interrupt register enables individual inter-
rupt events for each channel.
Channel 0:
Reserved OVR_EN INIT_EN TC_EN
76543210
Mnemonic: DMAEINT0 Address: FF29h
Channel 1:
Reserved OVR_EN INIT_EN TC_EN
76543210
Mnemonic: DMAEINT1 Address: FF3Dh
All values are read/writeable.
TC_EN, when set, enables the DMA interrupt to
indicate that the transfer counter reached its termi-
nal count (TC).
INIT_EN, when set, enables the DMA interrupt
upon initialization.
OVR_EN, when set, enables the DMA interrupt to
indicate that the pending requests counter ex-
ceeded 64K.
Cleared by a power-on reset or other device-wide
reset.
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Channel 0:
OVR INIT TC
76543210
Reserved
Mnemonic: DMAINT0 Address: FF2Ah
Channel 1:
OVR INIT TC
76543210
Reserved
Mnemonic: DMAINT1 Address: FF3Eh
TC, when set, indicates that the transfer counter
reached terminal count. This bit is cleared when
the INIT bit is set. This bit is set by hardware and
is cleared by software by writing a one. Writing a
zero has no effect. Used in conjunction with
TC_EN to flag an interrupt.
INIT, when set, indicates that initialization has oc-
curred. This bit is set by hardware and cleared by
software by writing a one. Writing a zero has no
effect. This bit is also cleared when software sets
the INIT bit in the corresponding channel's DMA
control register. Used in conjunction with INIT_EN
to flag an interrupt.
OVR, when set, indicates that the pending re-
quests counter has overflowed. This bit is set by
hardware and cleared by software by writing a one.
Writing a zero has no effect. This bit is also
cleared when the corresponding channel's pending
requests counter is cleared. Used in conjunction
with OVR_EN to flag an interrupt.
NOTE:
The OVR, INIT, and TC bits in the DMA
Status Register are cleared by writing a
‘1’ to their respective bit location. Writ-
ing a zero has no effect.
Cleared by a power-on reset or other device-wide
reset.
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Once a transfer is completed, the output of the
CRC register can be read by software, and the
signature can be compared with the expected
value.
DMA CRC Register (CRC[7:0])
CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0
76543210
Mnemonic: DMACRC_0 Address: FF48h
DMA CRC Register (CRC[15:8])
CRC15 CRC14 CRC13 CRC12 CRC11 CRC10 CRC9 CRC8
76543210
Mnemonic: DMACRC_1 Address: FF49h