Specifications

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O
O
u
u
t
t
p
p
u
u
t
t
P
P
a
a
t
t
h
h
C
C
h
h
a
a
r
r
a
a
c
c
t
t
e
e
r
r
i
i
s
s
t
t
i
i
c
c
s
s
The values listed below are representative, guideline values extracted from measured internal test pat-
terns. Actual values may depend on application-specific use. FastChip reports specific, worst-case guar-
anteed values in the Timing Analysis section of the project report.
All timing parameters assume worst-case operating conditions, including process technology, power sup-
ply voltage, and junction temperature. Values include delay driving one interconnect segment.
Guideline Guideline
Speed Grade -25 -40
Description Symbol Fig. Device Min Max Min Max Units
Propagation Delays
Output to Pad T
OP
36 All 8.7 5.5 ns
Output-enable to Pad high-
impedance (Hi-Z)
T
OPZ
36 All 12.2 8.5 ns
Output-enable to Pad active and
valid
T
OE
36 All 9.6 6.4 ns
PIO clock input on output register
(OREG) to Pad
T
KO
36 All 9.4 6.3 ns
PIO clock input on output-enable
register (OEREG) to Pad
T
KZ
36 All 15.1 9.9 ns
Setup Time before PIO clock CK
Output T
POSU
36 All 1.9 1.5 ns
Output-enable T
POOE
36 All 1.9 1.5 ns
Clock enable T
POEN
36 All 2.0 1.5 ns
Hold Time after PIO clock CK
All hold times T
PQH
36 All 0 0 ns
PIO Clock
Clock High time T
CHIO
36 All 2.5 2.5 ns
Clock Low time T
CLIO
36 All 2.5 2.5 ns
Guideline Guideline
批注 [SK32]: Used 8.7 out-
put to pad delay and added
3.5 ns
批注 [SK33]: Used 5.5 out-
put to pad delay and added
3.0 ns