Specifications

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B
B
u
u
s
s
C
C
l
l
o
o
c
c
k
k
a
a
n
n
d
d
G
G
l
l
o
o
b
b
a
a
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l
B
B
u
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f
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f
f
e
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r
r
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s
B
B
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C
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l
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B
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F
F
u
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c
c
t
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o
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a
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D
D
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a
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g
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r
a
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m
m
PAD
BCLK/XTAL
PAD
GBUFx
BusClock
GBufx
Figure 80. Bus Clock and Global Buffers.
B
B
u
u
s
s
C
C
l
l
o
o
c
c
k
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a
a
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d
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G
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a
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B
B
u
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f
f
f
f
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e
r
r
s
s
T
T
i
i
m
m
i
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n
n
g
g
C
C
h
h
a
a
r
r
a
a
c
c
t
t
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r
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G
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The values listed below are representative, guideline values extracted from measured internal test pat-
terns. Actual values may depend on application-specific use. FastChip reports specific, worst-case guar-
anteed values in the Timing Analysis section of the project report.
All timing parameters assume worst-case operating conditions, including process technology, power sup-
ply voltage, and junction temperature.
Guideline Guideline
Speed Grade -25 -40
Description Symbol Fig. Device Maximum Maximum
Units
Bus Clock
ZE502 5.7 4.3 ns
ZE505 5.7 4.3 ns
ZE512 5.7 4.3 ns
From BCLK/XTAL input through bus
clock buffer to any CSL or PIO clock
input CK [1]
T
BCLK
34
ZE520 5.7 4.3 ns
Global Buffers
ZE502 7.1 5.5 ns
ZE505 7.1 5.5 ns
ZE512 7.1 5.5 ns
From GBUFx input through associated
global buffer to any CSL or PIO input
[2]
T
GBUF
34
ZE520
7.1 5.5 ns
Guideline Guideline
Note 1:
Values for all devices based on data measured on a ZE520. The delays for the ZE502, ZE505, and
ZE512 are expected to be less than the ZE520.
批注 [SKK31]: All –25
numbers are –40 times 1.3