Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
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CK
WE
T
WS16,32
T
WP16,32
T
WH16,32
T
DS16,32
T
DH16,32
T
AS16,32
T
AH16,32
T
AO16,32
T
AO16,32
T
WO16,32
A[n:0]
DI
OLD NEW
O
Figure 76. Single-port RAM timing diagram.
WEA
WEB
T
WSDP
T
WPDP
T
WHDP
T
DSDP
T
DHDP
T
ASDP
T
AHDP
T
AODP
T
WODP
A[n:0]
B[n:0]
DA
DB
OLD NEW
OA
OB
CK
ERRIN
ERROUT
T
EODA
T
AODP
T
EIEO
T
EIEO
T
CKEO
Figure 77. Dual-port RAM timing diagram.