Specifications

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CNT23 CNT22 CNT21 CNT20 CNT19 CNT18 CNT17 CNT16
76543210
Mnemonic: DMACCNT0_2 Address: FF31h
Channel 1:
DMA Current Count Channel 1 (CNT[7:0])
CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0
76543210
Mnemonic: DMACCNT1_0 Address: FF43h
DMA Current Count Channel 1 (CNT[15:8])
CNT15 CNT15 CNT13 CNT12 CNT11 CNT10 CNT9 CNT8
76543210
Mnemonic: DMACCNT1_1 Address: FF44h
DMA Current Count Channel 1 (CNT[23:16])
CNT23 CNT22 CNT21 CNT20 CNT19 CNT18 CNT17 CNT16
76543210
Mnemonic: DMACCNT1_2 Address: FF45h
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Channel 0:
W/R- PAIR BLOCK
SFTREQ
CONT INIT EN CLR
76543210
Mnemonic: DMACTRL0_0 Address: FF27h
76543210
CRC_EN
ADRM1 ADRM0Reserved
Mnemonic: DMACTRL0_1 Address: FF28h
Channel 1:
W/R- PAIR BLOCK
SFTREQ
CONT INIT EN CLR
76543210
Mnemonic: DMACTRL1_0 Address: FF3Bh
76543210
CRC_EN
ADRM1 ADRM0Reserved
Mnemonic: DMACTRL1_1 Address: FF3Ch
All values are read/writeable.
CLR, when set, disables the DMA channel and
clears the transfer counter and pending requests
counter. Clearing the bit indicates that the DMA
channel is ready to operate. Cleared by reset.
EN, when set, enables the DMA request for the
channel. When this bit is set, the pending requests
counter is cleared and the DMA channel is ready
to accept requests. When this bit is cleared, in-
coming requests are ignored. Cleared by reset.
INIT, when set, initializes a DMA transfer. An ini-
tialization is associated with the transfer of each
block transfer. When this bit is set, the starting
operation values are loaded into their correspond-
ing counters at the beginning of a transfer. Once
the transfer has started, the bit is cleared by hard-
ware. Software can set it again during the current
block transfer to prepare the DMA channel for the
next block. When cleared, the DMA stops after the
current transfer. Cleared by reset.
CONT, when set, indicates continuous initialization
mode. When set, the DMA transfer on the current
block continues until this bit is cleared. Cleared by
reset.
SFTREQ, when set, requests a software-initiated
DMA transfer. This bit is cleared by hardware on
the following clock cycle.
BLOCK, when set, indicates block request mode.
When set, a complete block transfer is performed
by the DMA upon receiving a single request from a
device. Unaffected by reset.
PAIR, when set in both channels, couples the two
DMA channels to perform memory-to-memory
transfers. Unaffected by reset.
W/R- indicates the direction of the DMA transfer.
When set, the DMA performs a memory-to-I/O
transfer (DMA Write). When clear, the DMA per-
forms an I/O-to-memory transfer (DMA Read).
Unaffected by reset.
ADRM1 and ADRM0 define the transfer address
mode as shown below. Unaffected by reset.
Table 2. DMA Address Mode Settings.
ADRM1 ADRM0
Mode
0 0
Increment address by one
after each byte transfer
1 0
Decrement address by one
after each byte transfer
x 1
Single address transfer
(address remains con-
stant)
CRC_EN enables CRC checking. When set, this
bit activates the CRC logic. A 0-to-1 transition on
this bit resets the CRC logic to 0.
Cleared by a power-on reset or other device-wide
reset.
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This field indicates the number of DMA requests
yet to be serviced. Up to 64K requests can be re-
ceived ahead of their corresponding acknowledge.
Cleared by a power-on reset or other device-wide
reset.
The values are read-only.