Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 108
C
C
o
o
n
n
f
f
i
i
g
g
u
u
r
r
a
a
b
b
l
l
e
e
S
S
y
y
s
s
t
t
e
e
m
m
L
L
o
o
g
g
i
i
c
c
(
(
C
C
S
S
L
L
)
)
C
C
e
e
l
l
l
l
(
(
C
C
o
o
m
m
b
b
i
i
n
n
a
a
t
t
o
o
r
r
i
i
a
a
l
l
L
L
o
o
g
g
i
i
c
c
M
M
o
o
d
d
e
e
,
,
S
S
e
e
q
q
u
u
e
e
n
n
t
t
i
i
a
a
l
l
M
M
o
o
d
d
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)
)
In combinatorial mode, a single CSL cell implements any possible logic function of zero to four inputs.
Likewise, a single CSL cell behaves like a 16x1 read-only memory (ROM). The contents of the ROM are
loaded during initialization.
Two CSL cells operating in tandem implement any possible logic function of zero to five inputs. Likewise,
two CSL cells in tandem behave like a 32x1 read-only memory (ROM). The contents of the ROM are
loaded during initialization.
Two CSL cells operating in tandem also implement a limited number of logic functions of between six to
nine inputs.
Special logic allows the logic functions to be cascaded into wider functions.
In sequential mode, each CSL provides a 'D'-type, edge-triggered flip-flop with clock-enable control and
an asynchronous set or clear control.
C
C
S
S
L
L
C
C
o
o
m
m
b
b
i
i
n
n
a
a
t
t
o
o
r
r
i
i
a
a
l
l
L
L
o
o
g
g
i
i
c
c
a
a
n
n
d
d
S
S
e
e
q
q
u
u
e
e
n
n
t
t
i
i
a
a
l
l
M
M
o
o
d
d
e
e
F
F
u
u
n
n
c
c
t
t
i
i
o
o
n
n
a
a
l
l
D
D
i
i
a
a
g
g
r
r
a
a
m
m
s
s
4-input
LUT or
16x1 ROM
I3
I2
I1
I0
O
Flip-flop
D
EN
ASY
Q
WIDE4
CI
CO
Figure 66. Four-input logic function.
I4
I3
I2
I1
I0
O
5-input
LUT or
32x1 ROM
Flip-flop
D
EN
ASY
Q
WIDE5
CI
CO
Figure 67. Five-input logic function, requires
two CSL cells in tandem..
I4
I3
I2
I1
I0
6- to 9-input
logic function
I8
I5 O
Flip-flop
D
EN
ASY
Q
Figure 68. Six- to nine- input logic function,
requires two CSL cells in tandem.
D
EN
ASY
Q
Flip-flop
Figure 69. CSL cell flip-flop.