Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 106
Guideline Guideline
Speed Grade
-25 -40
Description Symbol Fig. Device Typical Typical
Units
Wait-State Control
Selector output valid (WrSel, RdSel, or Sel),
through LUT4, distributed and setup to WaitNext
T
CWNS
16 All 12.0  28.0 9.0  16.0 ns
Additional logic and interconnect delay allowed
in Selector path before WaitNext, operating at
maximum clock frequency, F
BCLK
T
BCYC -
T
CWNS
16 All 12.0  28.0 9.0  16.0 ns
CSL flip-flop output Q valid, through LUT4, dis-
tributed and setup to WaitNext
T
CWNQ
16 All 16.0  20.0 9.0 15.0 ns
Additional logic and interconnect delay allowed
in CSL flip-flop Q output path before WaitNext,
operating at maximum clock frequency, F
BCLK
T
BCYC -
T
CWNQ
16 All 20.0  24.0 10.0  16.0 ns
Waited output valid, through LUT4, distributed
and setup to CSL flip-flop
T
CWTD
16 All 12.0  28.0 7.0  15.0 ns
Additional logic and interconnect delay allowed
in Waited path before CSL flip-flop, operating at
maximum clock frequency, F
BCLK
T
BCYC -
T
CWTD
16 All 12.0  28.0 10.0  18.0 ns
Breakpoint Control
Selector output valid (WrSel, RdSel, or Sel),
through LUT4, distributed and setup to Break
T
CBPS
17 All 12.0  28.0 9.0  16.0 ns
Additional logic and interconnect delay allowed
in Selector path before Break, operating at
maximum clock frequency, F
BCLK
T
BCYC -
T
CBPS
17 All 12.0  28.0 9.0  16.0 ns
CSL flip-flop output Q valid, through LUT4, dis-
tributed and setup to Break
T
CBPQ
17 All 16.0  20.0 9.0 15.0 ns
Additional logic and interconnect delay allowed
in CSL flip-flop Q output path before Break, op-
erating at maximum clock frequency, F
BCLK
T
BCYC -
T
CBPQ
17 All 20.0  24.0 10.0  16.0 ns
Event output valid, through LUT4, distributed
and setup to CSL flip-flop
T
CEVT
17 All 12.0  28.0 7.0  15.0 ns
Additional logic and interconnect delay allowed
in Event path before CSL flip-flop, operating at
maximum clock frequency, F
BCLK
T
BCYC -
T
CEVT
17 All 12.0  28.0 10.0  18.0 ns
DMA Request/Acknowledge
PIO input valid, through LUT4, distributed and
setup to ReqSel
T
CRSP
18 All 17.0  25.0 10.0  15.0 ns
Additional logic and interconnect delay allowed
in PIO request path before ReqSel, operating at
maximum clock frequency, F
BCLK
T
BCYC -
T
CRSP
18 All 15.0  23.0 10.0  15.0 ns
CSL flip-flop output Q valid, through LUT4, dis-
tributed and setup to ReqSel
T
CRSQ
18 All 16.0  20.0 9.0 15.0 ns
Additional logic and interconnect delay allowed
in CSL flip-flop Q output path before ReqSel,
operating at maximum clock frequency, F
BCLK
T
BCYC -
T
CRSQ
18 All 20.0  24.0 10.0  16.0 ns
AckSel output valid, through LUT4, distributed
and setup to CSL flip-flop
T
CACK
18 All 12.0  28.0 7.0  15.0 ns
Additional logic and interconnect delay allowed
in AckSel path before CSL flip-flop, operating at
maximum clock frequency, F
BCLK
T
BCYC -
T
CACK
18 All 12.0  28.0 10.0  18.0 ns
Guideline Guideline