Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 104
CSI Bus
Socket
DQLUT4
WrSel, RdSel, Sel
Waited
Bus Clock
WaitNext
Figure 62. Wait-state control circuit.
CSI Bus
Socket
DQLUT4
WrSel, RdSel, Sel
Event
Bus Clock
Break
Figure 63. CSL Breakpoint control circuit.
CSI Bus
Socket
AckSel
ReqSel
Bus Clock
PIO
DQ
Figure 64. CSL DMA request/acknowledge circuit.