Specifications

103 www.zylogic.com.cn
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The Zylogic Configurable System Interconnect (CSI) bus socket provides a family-independent interface
between the processor, its peripherals, and the Configurable System Logic (CSL) matrix. The following
values provide a typical range of worst-case delays based on test designs. The actual values depend on
a variety of factors including how the CSL logic cells connect to the CSI bus in the application, the utiliza-
tion of the CSL matrix, and the number of modules in the design. The tables also show how much addi-
tional logic delay, or slack time, is allowed in each type of logic path while operating at the maximum bus
clock frequency,
F
BCLK
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32
Address
Data Write
8
DMA ReqSel
WaitNext
Break
Selector RdSel
Selector WrSel
ChipSel RdSel
ChipSel Sel
DMA AckSel
Waited
Event
Bus Clock
Data
Address
Selector
ChipSel
DMACtrl
WaitCtrl
BrkPnt
BusClk
8
Data Read
Enable
Figure 57. Configurable System Interconnect (CSI) bus socket.
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D
EN
Data Write
WrSel, Sel, AckSel
Bus Clock
Q
CSI Bus
Socket
8
Byte-Wide
Data Register
Figure 58. CSI bus write to byte-wide register.
4
DI
WE
Data Write
WrSel, Sel, AckSel
Bus Clock
O
CSI Bus
Socket
8
16x8 RAM
AAddress
Figure 59. CSI bus write to 16x8 RAM.
8
D
ENRdSel, Sel, AckSel
Q
CSI Bus
Socket
Byte-Wide
Data Register
Data Read
Enable
Figure 60. CSI bus read from byte-wide register.
4
8
Data ReadDI
WE
O
16x8 RAM
AAddress
EnableRdSel, Sel, AckSel
CSI Bus
Socket
Figure 61. CSI bus read from 16x8 RAM.