Specifications

Zylogic ZE5 Configurable System-on-Chip Platform
www.Zylogic.com.cn 100
E
E
x
x
a
a
m
m
p
p
l
l
e
e
M
M
e
e
m
m
o
o
r
r
y
y
I
I
n
n
t
t
e
e
r
r
f
f
a
a
c
c
e
e
U
U
n
n
i
i
t
t
(
(
M
M
I
I
U
U
)
)
W
W
a
a
v
v
e
e
f
f
o
o
r
r
m
m
s
s
C1 C2 C3 C4 C4 C1
BCLK
CE-
OE-
WE-
A[17:0]
D[7:0]
T
BCYC
T
BCH
T
BCL
T
MCEA
T
MCED
T
MOEA
T
MOED
T
MDRZ
T
MAH
T
MDSU
T
MAA
T
MCAD
T
MCER
T
MOEP
T
MCEO
ADDRESS
DATA
T
MDOE
T
MZOE
T
MADC
RSU RPW
Read Setup Time Read Pulse Width
Additional wait-states, if required
when using slower memories,
extend processor cycle C4
8032 internal
processor cycles
T
MRAC
Figure 55. 8032 instruction-fetch (read) from external memory via Memory Interface Unit (MIU). In
the figure, the read setup time is 1.5 Bus Clock cycles (RSU=1) and the read strobe
pulse width is asserted for 2.5 Bus Clock cycles (RPW=2). Note that the MIU extends
the microcontroller's C4 instruction cycle if the ZE5 is connected to a slow external
memory.
BCLK
CE-
OE-
WE-
A[17:0]
D[7:0]
T
BCYC
T
BCH
T
BCL
T
MCEA
T
MCED
T
MWEA
T
MDWH
T
MAH
T
MAA
T
MCAD
T
MCEW
ADDRESS
T
MWED
T
MWEP
T
MCWE
T
MDWA
T
MDWE
T
MDHW
T
MADC
DATA
T
MWEC
WSU
Write Setup Time
WPW
Write Pulse Width
WHT
Write Hold Time
Figure 56. MIU write cycle to external memory. In the figure, the write setup time is 1.5 Bus Clock
cycles (WSU=1), the write strobe pulse width is asserted for 1.5 Bus Clock cycles
(WPW=1), and the write data hold time is 1.0 Bus Clock cycles (WHT=1).