Zylogic ZE5 Configurable System-on-Chip Platform ® March, 2004 (Version 1.
Zylogic ZE5 Configurable System-on-Chip Platform Device ZE502 Table 1.
- Via JTAG using internal system RAM to store program code - 'Stealth'-mode operation from internal RAM during battery-backed operation Four-pin IEEE 1149.
Zylogic ZE5 Configurable System-on-Chip Platform JTAG Connector 16 +3.3V GND TMS TDI TDO TCK TMS TDI TDO PIO VCC PIO PIO SLAVEVSYS Triscend Configurable System-on-Chip (CSoC) PIO +3.3V PIO XTAL PIO PIO RST- 28 PIO PIO XTALIN GND PIO PIO Up to 125 PIO pins in 208-pin PQFP package +3.3V TCK PIO GND CE- WE- OE- D[7:0] A[17:0] 8 18 CE- WE- OE- D[7:0] A[17:0] Flash ROM 256Kx8 VCC GND +3.3V GND Figure 3. A complete Zylogic ZE520 Configurable System-on-Chip (CSoC) design.
executed from internal RAM, offering faster access plus security in battery-backed applications. debugging, the JTAG port also sets up the internal hardware breakpoint unit. The majority of the system, including the microcontroller, operates from a single bus-clock signal. Optional sources for the bus clock include driving it directly from an off-chip signal, connecting an external crystal or ceramic oscillator between the dedicated crystal-oscillator amplifier pins, or using the internal ring oscillator.
Zylogic ZE5 Configurable System-on-Chip Platform Bus Request/Grant Bus Request/Grant DMA Channel 0 DMA Channel 1 Control Logic Pending Requests Counter Transfer Counter Address Counter FIFO FIFO FIFO FIFO CRC Data Read Bus Address Bus and Data Write Bus Figure 4. Block diagram of the embedded two-channel DMA controller. Pow er Management Like the original 80C31, the ZE5 provides Idle and Power-Down modes of operation.
the DMA controller services the request. Software can detect that a transfer has been initiated when the INIT bit is cleared. The next transfer parameters can be updated and the INIT bit set. itself with a particular channel through a DMA control register (DMACTRL), which contains a request and acknowledge signal pair. The two DMA channels can also be paired to perform memory-tomemory operations. Requests are processed on a cycle basis.
Zylogic ZE5 Configurable System-on-Chip Platform can be combined to form more complex and powerful operations. PAIR bit in the control register of both channels enables this mode. Transfers are initiated using the master's control register. However, the slave channel must be enabled and its transfer parameters set correctly. Single Transfer Mode In this mode, the DMA initiates a single byte transfer for each request.
CRC signature can be compared with the expected value. Mnemonic: DMASADR0_0 Address: FF20h DMA Source Address Channel 0 (A[15:8]) The CRC logic uses a CRC-CCITT 16-bit divisor polynomial, as shown in the equation below. The algorithm is capable of detecting any one, two or an even number of bits in error as well as a large number of burst errors.
Zylogic ZE5 Configurable System-on-Chip Platform DMA Transfer Count Channel 0 (CNT[15:8]) 7 6 5 4 3 2 1 0 CNT15 CNT15 CNT13 CNT12 CNT11 CNT10 CNT9 CNT8 6 5 4 3 2 1 0 CNT23 CNT22 CNT21 CNT20 CNT19 CNT18 CNT17 CNT16 6 5 4 3 2 1 0 A22 A21 A20 A19 A18 A17 A16 Mnemonic: DMACADR0_2 Mnemonic: DMASCNT0_1 Address: FF25h DMA Transfer Count Channel 0 (CNT[23:16]) 7 7 A23 Address: FF2Dh DMA Current Address Channel 0 (A[31:24]) 7 6 5 4 3 2 1 0 A31 A30 A29 A28
7 6 5 4 3 2 1 0 CNT23 CNT22 CNT21 CNT20 CNT19 CNT18 CNT17 CNT16 Mnemonic: DMACCNT0_2 INIT, when set, initializes a DMA transfer. An initialization is associated with the transfer of each block transfer. When this bit is set, the starting operation values are loaded into their corresponding counters at the beginning of a transfer. Once the transfer has started, the bit is cleared by hardware.
Zylogic ZE5 Configurable System-on-Chip Platform DMA Status Register (one per channel) Channel 0: Channel 0: DMA Pending Requests Channel 0 (REQ[7:0]) 7 6 5 4 3 2 1 0 REQ7 REQ6 REQ5 REQ4 REQ3 REQ2 REQ1 REQ0 Mnemonic: DMAPREQ0_0 7 Address: FF32h 7 6 5 4 3 2 1 0 REQ14 REQ13 REQ12 REQ11 REQ10 REQ9 REQ8 Mnemonic: DMAPREQ0_1 7 6 5 4 3 2 1 0 REQ5 REQ4 REQ3 REQ2 REQ1 REQ0 Mnemonic: DMAPREQ1_0 6 5 4 3 2 1 0 REQ14 REQ13 REQ12 REQ11 REQ10 REQ9 REQ8 Mne
Cleared by a power-on reset or other device-wide reset. trol registers cover individual DMA read and write operations from both channels 0 and 1. Another DMA control register can be enabled via software after first disabling the active control register. Interfacing CSL Peripherals to the DMA Controller Distributed DMA Control Register This register is shared by both DMA channels.
Zylogic ZE5 Configurable System-on-Chip Platform Request to DMA Controller Configurable System Logic The remainder of the transaction is as shown Figure 8. DMA1 REQ 1. The requesting “soft” module asserts its REQSEL DMA request signal. Within the DMA control register, this incoming request is steered to the proper DMA channel. REQSEL DMA0 REQ SEL 2. The DMA channel requests the CSI bus from the bus arbiter. This process may require multiple clock cycles. ENBL DMA Select Register Figure 6.
Side-band Signals Hardware Breakpoint Unit Figure 9. Data Read Address Bus Clock DMA Request/ Acknowledge Wait-State Control Breakpoint Control Configurable System Logic (CSL) Matrix 2-Channel DMA Controller Data Write Selectors 8032 "Turbo" Microcontroller Configurable System Interconnect (CSI) Bus CSI Socket Interface The Configurable System Interconnect (CSI) bus and the socket interface to "soft" modules in the CSL matrix.
Zylogic ZE5 Configurable System-on-Chip Platform Data Write Data Read 8 8 Address 32 Selector Decode DMA Acknowledge CSL Logic Function Read Enable DMA ReqSel Bus Waited Wait Next Cycle Force Breakpoint Breakpoint Event Bus Clock Synchronous Interface Figure 10. The CSI bus socket represents a simple-to-use, synchronous interface to custom logic functions implemented in the CSL logic matrix. with the increasing size of the CSL matrix.
FastChip also defines the values initially loaded into the address mapper registers. Address Specification The MATCH0 and MATCH1 register values are automatically defined by the Zylogic FastChip development system at design time. These register values are not changed by application software. Address Selector Modes An address selector performs one of three potential functions as shown in Table 4. The addresses loaded into MATCH0 and MATCH1 are symbolically defined by the user during hardware design.
Zylogic ZE5 Configurable System-on-Chip Platform A2 A1 A0 A31 CSI Bus Address READ Match0: Addr. Bit = Low RDSEL Match1: Addr. Bit = High SEL WRITE BCLK In chip select mode, an address selector decodes any read or write transaction to the target address range. DMA Control A selector provides a relocatable control register for CSL “soft” modules requiring DMA access. The DMA control register enables requests and steers the request and acknowledge signals to the selected DMA channel.
WRSEL signal. The CSL “soft” module uses WRSEL to enable a register and capture the write data. trix may require wait-states, either because the “soft” module handshakes with another asynchronous device or if the “soft” module is too slow to respond in a single bus cycle. If a “soft” module requires any wait-states, a selector must assert the first wait-state. The selector will only assert a wait-state if the system is accessing the selector's target address space.
Zylogic ZE5 Configurable System-on-Chip Platform state and the “soft” module must assert the WAITNEXT signal to insert additional waitstates. onto the Data Read output bus, part of the CSI socket. Figure 18 shows an example transaction where the selected “soft” module uses the WAITNEXT signal to insert wait-states. During the first bus cycle, the addressed “soft” module's selector asserts it RDSEL output.
Timer 1 external input External I/O for Timer 2 Timer/Counter 2 capture/reload trigger or an additional external interrupt source if Timer 2 baudrate generator unused External Interrupt 0 External Interrupt 1 High-Priority Interrupt Serial port receive data input. Used in modes 1, 2, and 3. Serial port receiver output. Used in serial port mode 0 for shift clock.
Zylogic ZE5 Configurable System-on-Chip Platform TE532 (5x5) TE520 (4x4) TE512 (3x3) TE505 (2x2) TE502 (2x1) Figure 19. The five member of the ZE5 CSoC devic family range in density from two CSL banks (256 CSL cells) up to 25 CSL banks (3,200 CSL cells). Sideband Interface CSL Bank CSL Bank CSL Bank CSL Bank CSL Bank CSL Bank CSL Bank CSL Bank CSL Bank Vertical Breakers Horizontal Breakers Figure 20.
Selectors Vertical Breaker CSL Bank Adjacent CSL Cells Figure 21. A CSL bank consists of 8 columns by 16 rows of CSL cells, a 128 in total. Table 6. CSL Banks by Device. Part CSL Banks Number Columns Rows Total ZE502 2 1 2 ZE505 2 2 4 ZE512 3 3 9 ZE520 4 4 16 ZE532 5 5 25 Signals from one CSL bank can cross into other banks via the breakers, though crossing a breaker adds delay to the signal.
Zylogic ZE5 Configurable System-on-Chip Platform Selector outputs from vertical breaker Selector outputs from vertical breaker 4 Clock/Global Buffer Carry, cascaded wide function path 8 Short Segments CSL Cell 8 Long Lines CSL Cell 8 Short Segments Routing Matrix 8 Short Segments 4 Clock/Global Buffers 8 Long Lines 4 Clock/Global Buffers Address outputs from horizontal breaker Routing Matrix 8 Long Lines Routing Matrix Routing Matrix 8 Short Segments Carry, cascaded wide function path Figur
4 Multiplexer Chains for distributing bidirectional data across a CSL bank. The multiplexer chains behave much like a bidirectional, threestate bus but avoids the potential datacontention problems and associated power consumption of a three-state bus because all signals are unidirectional. General-purpose Interconnect The general-purpose interconnect, shown in Figure 22, distributes signals within a CSL bank.
CO Zylogic ZE5 Configurable System-on-Chip Platform O DI LUT I3 I3 I2 I2 I1 I1 I0 I0 Flip-Flop D O Q Q EN CARRY/ WIDE S/R EN CK ASYNC CI Programmed by initialization data Figure 26. A basic CSL cell of both combinatorial and sequential logic. possible function of five inputs. Two CSL cells also implement some functions of between six to nine inputs, with limitations. A sequence of four- or five-input functions, chained together, create wide gate functions of practically any width.
(X≥Y) 27 www.zylogic.com.
Zylogic ZE5 Configurable System-on-Chip Platform Table 9. Logic functions implemented in a CSL cell. CSL Function Cells Application f(4) Any combinatorial logic function with four or Any 1 less inputs. Includes any mixture of AND, 4-input logic NAND, OR, NOR, XOR, XNOR, and INVERT. Class function f(5) Any 5-input logic function Logic Some functions of 6 to 9 inputs Class 2 Any combinatorial logic function with five inputs. Includes any mixture of AND, NAND, OR, NOR, XOR, XNOR, and INVERT.
Class Table 11. Memory functions implemented in a CSL cell. CSL Function Cells Application RAM16x1 DI WE CK 16x1 RAM A3 A2 A1 A0 1 A 16-deep by one-bit wide, clocked write, random-access memory (RAM). 2 A 32-deep by one-bit wide, clocked write, random-access memory (RAM). 2 A 16-deep by one-bit wide, clocked write, dual-port RAM supporting simultaneous read and write operations from both ports.
Zylogic ZE5 Configurable System-on-Chip Platform A 16x1 ROM consumes a single CSL cell while a 32x1 requires two CSL cells operating in tandem. Single-Port RAM (RAM16X1, RAM32X1) As a single-port RAM, a CSL cell provides The ROM's initial contents are specified in the user's design, loaded during initialization, and cannot be changed during operation. Four address inputs for a 16x1 RAM block, five address inputs for a 32x1 block.
Output Enable D Q EN Drive Strength Output D Q EN PAD Input Flip-Flop/ Latch Registered Input Q D EN Input Hysteresis Delay Zero Hold Time Clock Enable BusMinder™ Clock Figure 27. Programmable Input/Output block (PIO). Programmable Input/Output (PIO) Pins Connecting a group of PIOs to the processor requires CSI socket resources, including connections to the Data Read and Data Write busses, plus one or two address selectors.
Zylogic ZE5 Configurable System-on-Chip Platform First, the ZE5 has a dedicated external memory interface, separate from the programmable I/O ports. Furthermore, there are no shared PIO pins, unless so specified in the users design. Consequently, an ZE5 design may have as many as 315 PIO pins, depending on the device and package offering. The user determines the number of ports addressable by the processor. manently enabled or selectively enabled using the common clock-enable input. Table 13.
PIO Output Side Output signals can be optionally inverted within the PIO, and can pass directly to the pad or be stored in an edge-triggered output flip-flop. left floating. An unused input might float unless tied to High or Low. In addition, an input connected to a bi-directional bus might float if the bus is three-stated (high impedance). A logical Low on the Output-Enable signal forces the output into a high-impedance state. Consequently, a PIO functions as a three-state output or bi-directional I/O.
Zylogic ZE5 Configurable System-on-Chip Platform JTAG Support Embedded logic attached to the PIOs contains test structures compatible with IEEE Standard 1149.1 for boundary-scan testing, permitting easy chip and board-level testing. Default, Configured State All unused but configured PIO blocks are programmed as inputs with the soft BusMinder’s pullup resistor enabled. This prevents unused PIO pins from floating.
The main features of the memory interface unit are: Support for a standard 256Kx8 external memory interface grammable to between 25 ns and 550 ns with a granularity of 25 ns, using a 40MHz bus clock. The following timing diagrams illustrate the options described earlier.
Zylogic ZE5 Configurable System-on-Chip Platform erated through the MIU. The OE- and WE- signals behave similar to the general case. Their leading edges are generated of the falling edge of the clock, and their trailing edges are generated of the rising edge of the clock. Therefore, one cycle reads or writes are possible. Using the WAITNEXT signal, the MIU knows if it has to extend the external command (OE- or WE-) or if it should end the current cycle and generate a new one.
SER_WR is used to program a FLASH- or EEPROM-based external serial sequential-access PROM. Cleared by a power-on reset or other device-wide reset. Table 16. Write Pulse-Width Time. Bus Clock WPW2 WPW1 WPW0 Cycles 0 0 0 0.5 0 0 1 1.5 0 1 0 2.5 0 1 1 3.5 1 0 0 4.5 1 0 1 5.5 1 1 0 6.5 7.5 1 1 1 (default) DMA_RD is a reserved MIU mode used during manufacturing. Leave this bit cleared. Cleared by a power-on reset or other device-wide reset. DMA_WR is a reserved MIU mode used during manufacturing.
Zylogic ZE5 Configurable System-on-Chip Platform mable, external, serial PROM. reset. RPW[2:0] specifies the pulse width of OE- during a memory read sequence. The actual pulse width is (RPW[2:0] + ½) * (system clock period). These three bits are set to all ones by a power-on reset or other device-wide reset, defaulting to the slowest setting. SDOUT_EN- is the external serial memory write data output enable.
0xFFFF External 8032 Logical Memory Spaces Program Memory code priority, top to bottom 0xFFFF 0 User Code 0xFF 0 32-bit External Physical Data Memory Memory 0xFF_FFFF Init. Code, Data, + Mappers shown by (XDATA) Header Indirect ExampleInternal memory map after initialization Code 0 Mappers CMAP1 points to CMAP2 the MIU if operating from Flash. Else CMAP1 points to internal RAM.
Zylogic ZE5 Configurable System-on-Chip Platform BLOCK_SIZE value. If the mapper is enabled and the two addresses compare, then the mapper presents the translated address on the CSI bus. The lower physical address bits consists of the masked bits from the logical address, A[15:0]. Because all zones are 256 bytes or larger, the lower-byte of the logic address, A[7:0], always maps directly to the translated address.
CSI physical address space 0 – 0xFFFF 0x1_0000 – 0x1_FFFF 0x2_0000 – 0x02_FFFF 0x3_0000 – 0x7_FFFF Table 20. Addresses Allocated to System Resources. 8032 Address zone (bytes) Description Notes 1K Internal ROM Accessible following a system reset ZE502=8K, ZE505=16K, Depends on Internal XDATA RAM ZE512=32K, ZE520=40K, device ZE532=64K 256 or CRU – system configuration 4K registers N.A.
Zylogic ZE5 Configurable System-on-Chip Platform C2 Operand Target Address C1, C2 – Fully programmable code mappers Code mapper C2 has the highest priority in case of an address overlap with other code mappers. C1 and C2 can be individually enabled. Following a system reset, mappers C1 and C2 are disabled. Mapper C0 is always enabled. The Zylogic initialization program assigns application dependent values to these mappers.
The D0 mapper has one programmable CRU register, DMAP0_TAR. The content of DMAP0_TAR is placed on the A[31:24] physical CSI bus address lines when a D0 matching event occurs. D0 is always enabled.
Zylogic ZE5 Configurable System-on-Chip Platform automatically at power-up. When cleared, the block size is reduced to 256 bytes. D5 Target Address (Mid Byte) 7 6 5 4 3 2 1 0 A23 A22 A21 A20 A19 A18 A17 A16 Mnemonic: DMAP5_TAR_1 SFR export mapper A Zylogic configurable system-on-chip user can create custom microcontroller “soft” modules using the on-chip Configurable System Logic (CSL) matrix.
Mnemonic: XMAP_TAR_1 Address: FE21h Fetch C1 Op-Code Fetch C0 Operand Fetch (Init. ROM) C0 Op-Code Fetch (Init.
Zylogic ZE5 Configurable System-on-Chip Platform Once a breakpoint condition occurs, then depending on its current configuration, the MCU freezes at the end of the current instruction or receives a breakpoint interrupt and branches to execute debugger interrupt routines. Following a breakpoint freeze, CSL clocks or global signals can be blocked to aid system debugging. The Zylogic FastChip software enables the user to specify which CSL clocks or global signals are affected following a breakpoint freeze.
(Top View) The JTAG port can also be used to initialize the CSoC or to update external memory devices connected to the MIU port. Using external Flash memory, the JTAG unit downloads a Flashprogramming algorithm to the CSoC’s internal RAM. It then interacts with the internal MCU, allowing the processor to control the actual program / erase / verify algorithms while the JTAG port supplies new data for programming or new series of commands required by the MCU. TDO 1 2 N.C. TDI 3 4 N.C. 5 6 N.C. +3.
Zylogic ZE5 Configurable System-on-Chip Platform Configuration Register Unit (CRU) In active initialization modes, the Zylogic ZE5 provides the control signals, directing data transfers and controlling external devices. The Configuration Register Unit (CRU) contains the control registers for functions within the Zylogic ZE5 configurable system-on-chip. For most applications, the CRU registers occupy the upper 256 bytes of external data space.
Passive Parallel Mode Once the system initialization is complete, the 8032 microcontroller starts executing application code from location 0000h, which is mapped to the external memory. Parallel mode requires that at least some application code reside in external memory. At the beginning of application program execution, code mapper C1 maps locations 0000H – 7FFFH of program space into the external memory. The user application code must initialize the data mappers and code mappers.
Zylogic ZE5 Configurable System-on-Chip Platform The serial memory interface requires only four interface signals. External Parallel Memory (Optional) CE- D0/SDIN - serial data bit from the serial PROM. A[x:0] Upper Address (optional) OE-/SRST - resets the serial memory to its starting location when High and enables the serial data output when Low. CE- - serial chip enable.
With the help of the microcontroller, the JTAG port can also program an external Flash memory. In the Flash programming mode, the JTAG unit downloads program / erase / verify algorithms into the internal RAM. The new Flash programming data can also be stored in the internal RAM. After the code and data mappers are properly defined via the JTAG port, the 8032 microcontroller can execute the program / erase / verify algorithms required to write new data into an external Flash memory device.
Zylogic ZE5 Configurable System-on-Chip Platform There is unrestricted write access to this register, a read is not required. Parallel Mode Secondary Initialization Program The secondary initialization program loads an ZE5 device with the initialization data. The initialization program consists of 8032 instructions.
is distributed globally to the CSL matrix and to the PIO pins. Table 28. Estimated Parallel Initialization Times at Various Bus Clock Frequencies. Bus Clock Frequency Device 1 MHz 5 MHz 25 MHz 40 MHz ZE502 94 ms 19 ms 4.5 ms 3.1 ms ZE505 112 ms 23 ms 5.2 ms 3.6 ms ZE512 181 ms 37 ms 8.0 ms 5.3 ms ZE520 265 ms 54 ms 11.4 ms 7.4 ms ZE532 364 ms 73 ms 15.3 ms 9.9 ms There are three potential user-defined sources for BCLK. 1.
Zylogic ZE5 Configurable System-on-Chip Platform C1 BCLK/XTAL XTAL BCLKSEL, when set, selects the crystal oscillator or an incoming, external clock source on the XTAL input pin. When cleared, then the internal ring oscillator provides the system clock. When the SLAVE- pin is Low, the BCLKSEL bit is forced to 1. BCLK R1 XTAL PWDSEL.4 Six Global Buffers In addition to system clock, there are six global signals available from within the CSL matrix.
ter, is also used in Multiply and Divide instructions. The ALU generates several status signals that are stored in the Program Status Word register (PSW). Serial Port The 8032 microcontroller provides one serial I/O port that operates in both synchronous and asynchronous modes. The serial port inhabits several SFR locations. Accumulator The Accumulator (ACC) is the primary register used in arithmetic, logical and data transfer operations in the configurable system-on-chip.
Zylogic ZE5 Configurable System-on-Chip Platform FFh Scratchpad RAM (Indirect Only) 80h 7Fh SFR (Direct Only) Direct RAM 30h 2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h 27h 26h 25h 24h 23h 22h 21h 20h 1Fh 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49
Special Function Registers The 8032 uses Special Function Registers (SFRs) to control and monitor peripherals and their modes. Data Pointer (Low Byte) The SFRs reside in the locations 80-FFh and are accessed by direct addressing only. Some of the SFRs are bit addressable. This allows a program to modify a particular bit without changing the others. The bit-addressable SFRs are those with addresses that end in 0 or 8. The 8032 "Turbo" microcontroller contains all the SFRs present in the original 8032.
Zylogic ZE5 Configurable System-on-Chip Platform instructions using DPTR will then access DPL1 and DPH1 in place of DPL and DPH. If DPL1/DPH1 are not used, then they can be used an conventional register locations. cution is halted. While in power-down mode, additional low-power options are enabled, controlled by the PWDSEL. See "Clocking and Global Signal Distribution" for more details. The DPL1 SFR is reset to 00h by a reset.
the interrupt was edge triggered. Otherwise, it tracks the value that appears the INIT0 sideband signal. The TL1 SFR is set to 00h on any reset. IT0 is the Interrupt 0 type control bit. It is set by software to specify a rising-edge trigger, cleared to specify an active-High level-triggered external input. Timer 0 MSB Mnemonic: TH0 There is unrestricted read/write access to this SFR. TH0.7-0 is the most-significant byte of Timer 0. The TH0 SFR is set to 00h on any reset.
Zylogic ZE5 Configurable System-on-Chip Platform RB8 is the received 9th data bit in Modes 2 and 3. In mode 1, if SM2 = 0, RB8 is the received stop bit value. In Mode 0, it has no function. T1M is the Timer 1 clock select bit. When T1M is set to 1, Timer 1 uses a divide-by-4 clock. When set to 0, Timer 1 uses an 8032-compatible divideby-12 clock. TI is the Transmit interrupt flag.
must be immediately followed by a write of 55h to TA. This opens a window for three machine cycles, during which time software can write to these protected bits. SADDR is used only during multiple MCU operations involving the serial port. SADDR is loaded with the given or broadcast address for the serial port if the ZE5 is used as a slave processor during multiprocessor communications. The TA returns FFh when read. The SADDR SFR is set to 00h by a reset.
Zylogic ZE5 Configurable System-on-Chip Platform The equation for controlling the baud rate is shown below, where {RCAP2H,RCAP2L} represent a 16bit binary value, F is the bus clock frequency, and Baud is the desired rate. Timer 2 by clearing this bit preserves the current count value in TH2, TL2. C/T2 is the Counter/Timer select bit. This bit determines whether Timer 2 functions as a timer (counting clock cycles) or as a counter.
F0 is User flag 0, a general-purpose flag that can be set or cleared by the user by software. cannot be accidentally overwritten by an errant program. Before attempting to change the RWT, EWT, WDIF, or POR bits, you must write the proper sequence to the Timed Access (TA) register. RS.1-0 select the active Register bank as shown in Table 34. WDIF is the Watchdog Timer Interrupt Flag. If the watchdog interrupt is enabled, hardware sets this bit to indicate that a watchdog interrupt occurred.
Zylogic ZE5 Configurable System-on-Chip Platform to the number of operands required by the instruction. Jumps and calls require an additional cycle to calculate the new address. Overall, the 8032 "Turbo" microcontroller reduces the number of dummy fetches and wasted cycles, thereby improving efficiency compared to the original 8032. Extended Interrupt Enable 7 6 5 4 3 2 1 0 - - - EWDI - - - - Mnemonic: EIE Address: E8h EIE.7-5 are reserved bits and return a High when read. EIE.
The bits in these SFRs are addressed by adding the bit position to the SFR address. MOVX @R0, A ; Moves the Accumulator contents to the ; external Data Memory locations pointed to ; by R0 in the page pointed to by the P2 ; SFR. MOVX A, @DPTR ; Move data from the Data Memory pointed : to by the selected Data Pointer, into the : Accumulator. Immediate Addressing Immediate addressing is used when part of the opcode instruction is a constant.
Zylogic ZE5 Configurable System-on-Chip Platform The Timer 2 interrupt is generated by a logical OR of the TF2 and the EXF2 flags. These flags are set by overflow/underflow or capture/reload events in the Timer 2 operation. The hardware does not clear these flags when a Timer 2 interrupt is executed. Software has to resolve the cause of the interrupt between TF2 and EXF2 and clear the appropriate flag.
3. The current instruction does not involve a write to IP, IE, EIP or EIE registers and is not a RETI. rupt. However there is a predefined hierarchy among the interrupts themselves. This hierarchy helps the interrupt controller to resolve simultaneous requests having the same priority level. The default hierarchy is defined as shown Table 35. The interrupts are numbered starting from the highest priority to the lowest.
Zylogic ZE5 Configurable System-on-Chip Platform LCALL. The vector addresses for the different sources are as shown in Table 37 Note that the vector addresses are not evenly spaced in memory. Execution continues from the vectored address until an RETI instruction is executed. On executing the RETI instruction, the processor pops the Stack and loads the PC with the contents at the top of the stack.
For example, a Power-On Reset (POR) condition resets all of the device functions including the 8032 “Turbo” microcontroller, peripherals connected to the internal CSI bus, many of the internal system registers (CRU), the clock logic, and the JTAG unit. From the time an interrupt source is activated, the longest response time is 12 machine cycles.
Zylogic ZE5 Configurable System-on-Chip Platform JTAG-initiated condition is cleared once the command is no longer asserted. System Behavior after a Reset Event After a reset event, the system either re-initializes and re-starts code execution or just re-starts code execution, depending on the type of reset event. Re-Initialization Following some types of resets, as shown in Table 39, the CSoC starts or re-starts the device initialization process.
SFR Name TCON TH0 TH1 TH2 TL0 TL1 TL2 TMOD Pow er Management The Zylogic ZE5 configurable system-on-chip has a built-in power-on reset system. This ensures that if the power levels are below the VRST level, the device is forced into the reset state. When power is turned on—such as during a cold reset— the device is reset automatically and remains so as long as VCC is less that VRST. Similarly, when power falls below VRST, the device is automatically reset.
Zylogic ZE5 Configurable System-on-Chip Platform GBUF, when set, signals the six global buffers when a power-down event occurs. Each global buffer has individual control bits that define its behavior during a power down or breakpoint event. After a reset condition, the program counter is reset to 0000h and all the SFRs are set to the reset condition. Because the clock is already running, there is no delay and execution starts immediately.
ured as a level-sensitive interrupt. An external reset causes the device to exit the Power down state. The Low on RST- pin terminates the Power Down mode, and restarts the clock. In the Power down mode, all clocks are stopped, so the Watchdog timer cannot be used to provide the reset to exit Power down mode. The Power on/fail reset, however, provides reset if power falls below the threshold level of VRST. crystal and set the MIU read timing parameters to the pre-power-down values.
Zylogic ZE5 Configurable System-on-Chip Platform 1. Life support devices or systems are devices which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. an interrupt service routine (ISR) for the corresponding external interrupt.
Added information about pin directionality during initialization to Pin Description. Added additional information on the VSYS and SLAVE- pins to Pin Description. Added information on using TH1 to control the baud rate for the serial port. See Timer 1 MSB. Added information on using RCAP2H and RCAP2L to control the baud rate for the serial port. See Timer 2 Capture LSB and Timer 2 Capture MSB. Added details to 5-volt tolerant PIO support. See 5Volt Tolerant I/Os.
Zylogic ZE5 Configurable System-on-Chip Platform Pin Description Table 43 describes the pins available on an ZE5 configurable system-on-chip device. The directionality of each pin is described for parallel, serial, and slave mode initialization. O=output. I=input. I (pullup)=input pin with soft pull-up during initialization—pin appears to float High. Table 43. Pins available on an ZE5 configurable system-on-chip and their function.
Pin Name Pin Description Parallel Ground connection for I/O functions; connect to ground GNDIO I for internal logic. All must be connected. N.C. No connect. There is no function on this pin. N.C. Active-Low output-enable signal. An output when the configurable system-on-chip accesses external memory OE-/SRST O during initialization in parallel or serial modes. An input while in slave mode. General-purpose input, output, or bi-directional signal pin after initialization is complete.
Zylogic ZE5 Configurable System-on-Chip Platform Pin Name TMS Pin Description JTAG Test Mode Select input. Tie High if unused. www.Zylogic.com.
Pin Name VCC VCCIO VSYS WE-/SEN- XTALIN Pin Description Parallel Supply voltage for internal logic functions, separate from I/O. Connect to a +3.3 volt supply. All must be conI nected and each must be decoupled with a 0.01 to 0.1 µF capacitor to ground. Supply voltage for I/O functions, separate from internal logic. Connect to a +3.3 volt supply. All must be conI nected and each must be decoupled with a 0.01 to 0.1 µF capacitor to ground. External 'system voltage-good' indicator input.
Zylogic ZE5 Configurable System-on-Chip Platform 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 1 96 2 95 3 94 4 93 5 92 6 91 7 90 8 89 9 88 10 87 TE502S08L 11 12 86 85 13 84 14 83 15 82 TE505S16L 16 17 81 80 18 79 19 78 20 77 21 76 TE512S32L 22 23 75 74 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 GNDIO PIO PIO PIO PIO/GBUF5 G
128-pin thin PQFP (Package Code=L) Package Pinout Tables Shaded cells represent a pin that is not connected on the ZE502 device but is a PIO pin for all other devices. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 ZE502 GNDIO XTALIN BCLK/XTAL TDI TDO TCK TMS PIO/A18 PIO/A19 GNDIO PIO PIO PIO/A20 PIO/A21 N.C. N.C. VCCIO GNDIO PIO/A22 PIO/A23 PIO/A24 PIO/A25 PIO/A26 PIO/A27 GNDIO N.C. N.C.
Zylogic ZE5 Configurable System-on-Chip Platform 128-Pin LQFP Pins by Type Parallel Mode Type PIO* VCC VCCIO GND GNDIO D[7:0] A[17:0] JTAG N.C. Others ZE502 52 3 8 3 16 8 18 4 8 8 Serial Mode ZE505 ZE512 60 3 8 3 16 8 18 4 0 8 Type PIO* VCC VCCIO GND GNDIO SDIN SCLK JTAG N.C. Others ZE502 ZE505 ZE512 76 3 8 3 16 1 1 4 8 8 84 3 8 3 16 1 1 4 0 8 PIO* includes pure PIO pins and those with alternate functions www.Zylogic.com.
128-pin thin PQFP (Package Code=L) Package Mechanical Draw ing D D1 128 97 1 θ1 96 θ2 Pin 1 Identifier Top View E1 E c θ 32 65 33 b e 64 S θ3 L L1 Detail 'A' A A2 See Detail 'A' A1 Symbol A A1 A2 b c D D1 E E1 e L L1 S θ θ1 θ2 θ3 Millimeters Nom. Max. — 1.60 — — 1.40 1.45 0.18 0.23 — 0.20 16.00 16.15 14.00 14.10 16.00 16.15 14.00 14.10 0.40 BSC 0.45 0.60 0.75 1.00 REF 0.20 — — 0º 3.5º 7º 0º — — 12º TYP 12º TYP Min. — 0.05 1.35 0.13 0.09 15.85 13.90 15.85 13.90 1.
Zylogic ZE5 Configurable System-on-Chip Platform GNDIO XTALIN BCLK/XTAL TDI TDO TCK TMS PIO/A18 PIO/A19 GNDIO PIO PIO PIO/A20 PIO/A21 (N.C.) PIO (N.C.) PIO (N.C.) PIO VCCIO GNDIO PIO/A22 PIO/A23 (N.C.) PIO (N.C.) PIO VCC GND PIO/A24 PIO/A25 GNDIO PIO/A26 PIO/A27 (N.C.) PIO (N.C.) PIO (N.C.) PIO (N.C.) PIO (N.C.) PIO (N.C.) PIO VCCIO GNDIO PIO/ A28 PIO/ A29 (N.C.) PIO (N.C.) PIO (N.C.) PIO (N.C.
208-pin PQFP (Package Code=Q) Package Pinout Tables Shaded cells represent a pin that is not connected on the ZE505 device but is connected on all other devices. ZE512 ZE520 Pin ZE505 ZE532 GNDIO 1 GNDIO XTALIN 2 XTALIN BCLK/ BCLK/ 3 XTAL XTAL TDI 4 TDI TDO 5 TDO TCK 6 TCK TMS 7 TMS 8 PIO/A18 PIO/A18 9 PIO/A19 PIO/A19 GNDIO 10 GNDIO 11 PIO PIO 12 PIO PIO 13 PIO/A20 PIO/A20 14 PIO/A21 PIO/A21 15 N.C. PIO 16 PIO PIO 17 PIO PIO VCCIO 18 VCCIO GNDIO 19 GNDIO 20 PIO/A22 PIO/A22 21 PIO/A23 PIO/A23 22 N.C.
Zylogic ZE5 Configurable System-on-Chip Platform ZE512 ZE520 Pin ZE505 ZE532 SLAVE151 SLAVE152 OE-/SRST OE-/SRST CE153 CERST154 RSTVSYS 155 VSYS VCCIO 156 VCCIO GNDIO 157 GNDIO 158 A0/SCLK A0/SCLK 159 A1/PIO A1/PIO 160 A2/PIO A2/PIO 161 A3/PIO A3/PIO 162 N.C. PIO GNDIO 163 GNDIO 164 A4/PIO A4/PIO 165 A5/PIO A5/PIO 166 A6/PIO A6/PIO 167 A7/PIO A7/PIO 168 PIO PIO 169 PIO PIO 170 N.C. PIO 171 N.C. PIO VCCIO 172 VCCIO GNDIO 173 GNDIO 174 N.C. PIO 175 N.C.
208-pin PQFP (Package Code=Q) Package Mechanical Draw ing D D1 208 157 156 1 Pin 1 Identifier θ1 Top View E1 E θ2 c θ 105 52 S 53 e 104 b θ3 L L1 Detail 'A' A A2 A1 See Detail 'A' Symbol A A1 A2 b c D D1 E E1 e L L1 S θ θ1 θ2 θ3 Millimeters Nom. Max. — 4.07 — — 3.23 3.30 — 0.28 — 0.23 30.60 30.85 28.00 28.10 30.60 30.85 28.00 28.10 0.50 BSC 0.35 0.50 0.65 1.30 REF 0.20 — — 0º — 7º 0º — — 12º TYP 12º TYP Min. 3.92 0.25 3.15 0.18 0.13 30.35 27.90 30.35 27.90 1.
Zylogic ZE5 Configurable System-on-Chip Platform 128-pin LQFP and 208-pin PQFP Land Pattern Dimensions C Y E X Full radius optional D Grid placement courtyard Symbol Z G X Y C D E www.Zylogic.com.cn G Z D 128-pin LQFP (Code=L) Min Ref Max — — 16.8 13.6 — — — — 0.25 — 1.6 — — 15.2 — — 12.4 — — 0.4 — 88 208-pin PQFP (Code=Q) Min Ref Max — — 30.8 27.6 — — — — 0.3 — 1.6 — — 29.2 — — 25.5 — — 0.
484-ball Ball-Grid Array Package, top view through top of package (Package Code=B) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A GNDIO A16/ PIO PIO PIO N.C. PIO PIO A12/ PIO PIO PIO A10/ PIO PIO N.C. A9/ PIO A8/ PIO PIO PIO PIO PIO PIO PIO PIO PIO A0/ CE- WE-/ B XTAL IN PIO A15/ A14/ PIO PIO PIO N.C. PIO N.C. N.C. PIO A11/ PIO PIO N.C. N.C. N.C.
Zylogic ZE5 Configurable System-on-Chip Platform 484-ball Ball-Grid Array (Package Code=B) Package Pinout Tables Shaded cells represent a pin that is a no connect for the ZE520 but may be a PIO pin for larger devices. Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 Pin Name GNDIO A16/PIO PIO PIO N.C. PIO PIO A12/PIO PIO PIO A10/PIO PIO N.C.
Ball M17 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N10 N11 N12 N13 N14 N15 N16 N17 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P10 P11 P12 P13 P14 P15 P16 P17 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R10 R11 R12 R13 R14 R15 R16 R17 R22 R23 R24 Pin Name GNDIO GNDIO GNDIO N.C. N.C. PIO PIO N.C. N.C. VCC VCC GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GND GND PIO PIO PIO PIO/A24 PIO/A25 N.C. GND GND GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO GNDIO VCC VCC PIO PIO PIO N.C. N.C. N.C.
Zylogic ZE5 Configurable System-on-Chip Platform Ball AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Pin Name PIO/GBUF1 PIO N.C. PIO PIO PIO PIO PIO PIO/A30 PIO PIO PIO/GBUF5 PIO PIO PIO/GBUF4 PIO PIO PIO PIO N.C. PIO N.C. PIO PIO PIO PIO PIO N.C. PIO N.C. PIO PIO PIO PIO 484-pin BGA Balls by Type Parallel Mode Type PIO* VCC VCCIO GND GNDIO D[7:0] A[17:0] JTAG N.C.
A1 Corner Index 484-pin BGA (Package Code=B) Package Mechanical Drawing Top View b E3 E2 E Detail 'A' ddd c D3 D2 Detail 'B' D A e AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A A1 Bottom View See Detail 'A' E1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 See Detail 'B' A2 D1 Symbol A A1 A2 b c D D1 D2 Min. 2.03 0.40 1.12 0.50 0.51 26.80 — 23.80 Millimeters Nom. Max. 2.23 2.43 0.50 0.60 1.17 1.22 0.60 0.70 0.56 0.61 27.00 27.20 25.00 — 24.00 24.
Zylogic ZE5 Configurable System-on-Chip Platform Electrical and Timing Characteristics Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL TJ Parameter Supply voltage relative to GND Input voltage relative to GND [1] Voltage applied to three-state output [1] Storage temperature (ambient) Maximum soldering temperature (10 s at 1/16 in. = 1.5 mm) Junction temperature, plastic packages Min -0.5 -0.5 -0.5 -60 Max 4.0 6.5 5.5 +150 Units V V V °C +260 °C +125 °C Max 3.6 +85 +100 200 30% VCC 5.
Note 7: Capacitance and inductance is sample-tested only. Zylogic ZE5 Switching Characteristic Guidelines All Zylogic devices are 100% functionally tested. These parameters are modeled after the testing methods described by MIL-M-38510/605. The values listed below are representative, guideline values extracted from measured internal test patterns. Actual values may depend on application-specific use.
Zylogic ZE5 Configurable System-on-Chip Platform JTAG Interface Timing Characteristics TJBSN TJBUS TJCH TJCL TCK TJMH TJMSU TMS TJDH TJDSU TDI TJCKO TDO Figure 47. JTAG timing diagram.
Description Symbol Bus Clock Input (BCLK/XTAL) pad to output delay using output flip-flop. TBPCO Speed Grade All -25 -40 Device Min [1] Max Max ZE502 2.0 24.0 17.5 ZE505 2.0 24.0 17.5 ZE512 2.0 24.0 17.5 2.0 24.0 17.5 ZE520 Preliminary Units ns ns ns ns Note 1: Not tested. Guaranteed by design. Bus Clock Input to Output Enable Delay OEFF PIO BusClock BCLK/XTAL 12 mA 35 pF Figure 49. Bus Clock to Output from output flip-flop, 12 mA driver.
Zylogic ZE5 Configurable System-on-Chip Platform flop or latch using the Bus Clock Input as clock, delayed input path. ZE505 ZE512 ZE520 4.5 6.0 4.5 6.0 4.5 6.0 Preliminary ns ns ns Global Buffer Input to Output Delay OUTFF Global Buffer 12 mA PIO 35 pF GBUFx Figure 51. Global Buffer clock to Output from output flip-flop, 12 mA driver. Description Symbol Global Buffer (GBUFx) pad to output delay using output flip-flop. TGPCO Speed Grade All -25 -40 Device Min [1] Max Max ZE505 2.0 23.0 17.
Global Buffer, Input Set-Up and Hold INFF PIO Global Buffer GBUFx Figure 53. PIO setup to input flip-flop before Global Buffer clock. Description Set-Up: Delayed Input Data set-up time before active clock edge to input flip-flop or latch using a Global Buffer as clock, delayed input path. Set-Up: No Delayed Input Data set-up time before active clock edge to input flip-flop or latch using a Global Buffer as clock, no delayed input path.
Zylogic ZE5 Configurable System-on-Chip Platform Example Memory Interface Unit (MIU) Waveforms Additional wait-states, if required when using slower memories, extend processor cycle C4 8032 internal processor cycles TC1 BCYC C2 C3 TBCH C4 TBCL C4 C1 BCLK TMOEA TMCEA TMCED TMCER CETMCEO TMOED TMOEP OETMRAC WE- TMCAD TMDOE TMADC TMAH TMAA ADDRESS A[17:0] TMDSU TMDRZ DATA D[7:0] RSU Read Setup Time RPW Read Pulse Width TMZOE Figure 55.
Memory Interface Unit (MIU) Timing Characteristic Guidelines, Stand-alone Operation (SLAVE- = High) All Zylogic devices are 100% functionally tested. These parameters are modeled after the testing methods described by MIL-M-38510/605. Pin-to-pin timing parameters are derived by measuring external and internal test patterns. The values listed below are representative for typical pin locations and normal clock loading. For these tests, Bus Clock is supplied externally via the BCLK pin.
Zylogic ZE5 Configurable System-on-Chip Platform Asynchronous Memory Interface Timing The following values are derived from MIU tests where Bus Clock is provided via an external source. While using the internal crystal oscillator amplifier or the internal ring oscillator, Bus Clock may not be externally visible. The following values provide relative timing referencing only signals available on the MIU.
Configurable System Interconnect (CSI) Socket Timing Guidelines The Zylogic Configurable System Interconnect (CSI) bus socket provides a family-independent interface between the processor, its peripherals, and the Configurable System Logic (CSL) matrix. The following values provide a typical range of worst-case delays based on test designs.
Zylogic ZE5 Configurable System-on-Chip Platform WrSel, RdSel, Sel Waited LUT4 D Q WaitNext Bus Clock CSI Bus Socket Figure 62. Wait-state control circuit. WrSel, RdSel, Sel Event LUT4 D Q Break Bus Clock CSI Bus Socket Figure 63. CSL Breakpoint control circuit. PIO D Q ReqSel AckSel Bus Clock CSI Bus Socket Figure 64. CSL DMA request/acknowledge circuit. www.Zylogic.com.
CSI Socket Timing Characteristic Guidelines The values listed below are representative, guideline values extracted from measured internal test patterns. Actual values may depend on application-specific use. FastChip reports specific, worst-case guaranteed values in the Timing Analysis section of the project report.
Zylogic ZE5 Configurable System-on-Chip Platform Description Wait-State Control Selector output valid (WrSel, RdSel, or Sel), through LUT4, distributed and setup to WaitNext Additional logic and interconnect delay allowed in Selector path before WaitNext, operating at maximum clock frequency, FBCLK CSL flip-flop output Q valid, through LUT4, distributed and setup to WaitNext Additional logic and interconnect delay allowed in CSL flip-flop Q output path before WaitNext, operating at maximum clock frequency,
Sideband Signal Timing Characteristics The sideband signals are controls to and from the embedded 8032 "Turbo" microcontroller, unique to the Zylogic ZE5 family. Each signal is associated with a specific dedicated resource inside the 8032 microcontroller. The values below indicate the number of Bus Clock cycles required for the signal to be recognized by the microcontroller.
Zylogic ZE5 Configurable System-on-Chip Platform Configurable System Logic (CSL) Cell (Combinatorial Logic Mode, Sequential Mode) In combinatorial mode, a single CSL cell implements any possible logic function of zero to four inputs. Likewise, a single CSL cell behaves like a 16x1 read-only memory (ROM). The contents of the ROM are loaded during initialization. Two CSL cells operating in tandem implement any possible logic function of zero to five inputs.
CSL Combinatorial Logic and Sequential Mode Timing Characteristic Guidelines The values listed below are representative, guideline values extracted from measured internal test patterns. Actual values may depend on application-specific use. FastChip reports specific, worst-case guaranteed values in the Timing Analysis section of the project report. All timing values shown assume worst-case operating conditions, including process technology, power supply voltage, and junction temperature.
Zylogic ZE5 Configurable System-on-Chip Platform Configurable System Logic (CSL) Cell (Arithmetic Mode) In arithmetic mode, a CSL implements a single bit preloadable adder or subtracter. Alternatively, a CSL implements a single-bit adder/subtracter with a separate add/subtract control. As a single-bit multiplier, a CSL cell has a partial-sum input from the previous multiplier stage. As with combinatorial logic, the outputs from an arithmetic function can be stored in the CSL cell's flip-flop.
Configurable System Logic (CSL) Cell (Memory Mode, Single-Port RAM) In memory mode, a single CSL cell implements a 16x1, edge-triggered, single-port random-access memory (RAM). Two CSL cells in tandem operate as a 32x1, edge-triggered RAM. The outputs can be captured in the CSL cell's flip-flop. CSL Memory Mode, Single-Port RAM Functional Diagrams 16x1 RAM 32x1 RAM DI WE CK DI WE CK O O A4 A3 A2 A1 A0 A3 A2 A1 A0 Figure 74. 16x1 single-port RAM. Figure 75. 32x1 single-port RAM.
Zylogic ZE5 Configurable System-on-Chip Platform TWP16,32 CK TWS16,32 TWH16,32 TDS16,32 TDH16,32 TAS16,32 TAH16,32 WE DI A[n:0] TWO16,32 TAO16,32 OLD O TAO16,32 NEW Figure 76. Single-port RAM timing diagram. TWPDP CK TWSDP TWHDP TDSDP TDHDP TASDP TAHDP WEA WEB DA DB A[n:0] B[n:0] OA OB TWODP TAODP TAODP OLD NEW ERRIN TEIEO TEIEO TCKEO ERROUT Figure 77. Dual-port RAM timing diagram. www.Zylogic.com.
Configurable System Logic (CSL) Cell (Memory Mode, Dual-Port RAM) In memory mode, two CSL cell in tandem implement a 16x1, edge-triggered, dual-port random-access memory (RAM). The outputs can be captured in a flip-flop. Built-in circuitry flags an error when writing both ports with different data, at the same address. CSL Memory Mode, Dual-Port RAM Functional Diagram 16x1 dual-port RAM DA OA WEA A3 A2 A1 A0 CK OB DB WEB B3 B2 B1 B0 ERROUT ERRIN Figure 78. 16x1 dual-port RAM.
Zylogic ZE5 Configurable System-on-Chip Platform Configurable System Logic (CSL) Cell (Memory Mode, 8-bit Shift Register) In memory mode, a CSL cell implements an 8-bit, serial-in/serial-out, preloadable shift register with clockenable control and tap select control. CSL Memory Mode, 8-bit Shift Register Functional Diagram 8-bit Shift Register SDO DI SH EN CK O A2 A1 A0 SDI Figure 79. 8-bit Shift Register.
Bus Clock and Global Buffers Bus Clock and Global Buffers Functional Diagram BCLK/XTAL PAD GBUFx PAD BusClock GBufx Figure 80. Bus Clock and Global Buffers. Bus Clock and Global Buffers Timing Characteristic Guidelines The values listed below are representative, guideline values extracted from measured internal test patterns. Actual values may depend on application-specific use. FastChip reports specific, worst-case guaranteed values in the Timing Analysis section of the project report.
Zylogic ZE5 Configurable System-on-Chip Platform Programmable Input/Output (PIO) Timing Guidelines Output Enable D Q EN Drive Strength Output D Q EN PAD Input Flip-Flop/ Latch Registered Input Q D EN Delay Zero Hold Time Clock Enable Input Hysteresis BusMinder™ Clock Figure 81. Programmable Input/Output (PIO). Input Path Characteristics The values listed below are representative, guideline values extracted from measured internal test patterns. Actual values may depend on application-specific use.
Output Path Characteristics The values listed below are representative, guideline values extracted from measured internal test patterns. Actual values may depend on application-specific use. FastChip reports specific, worst-case guaranteed values in the Timing Analysis section of the project report. All timing parameters assume worst-case operating conditions, including process technology, power supply voltage, and junction temperature. Values include delay driving one interconnect segment.
Zylogic ZE5 Configurable System-on-Chip Platform Output Buffer Switching Characteristics 60 IOL Output Current (mA) 50 40 30 20 IOH 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Output Voltage (V) Figure 82. 12 mA output buffer characteristics (TJ= 25ºC, VCCIO=3.3 Volts), HSpice simulation. 40 IOL Output Current (mA) 30 20 IOH 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Output Voltage (V) Figure 83. 12 mA output buffer characteristics (TJ= 85ºC, VCCIO=3.0 Volts), HSpice simulation. www.Zylogic.com.
Ordering Information Device Type TE502S08 TE505S16 TE512S32 TE520S40 TE532S64 TE5 20 S 40 - 40 Q C Triscend E5 Configurable System-on-Chip Family Temperature Range C = Commercial I = Industrial Package Style Configurable System Logic (CSL) Cells x 100 L = 128-pin Plastic Quad Flat Pack Q = 208-pin Plastic Quad Flat Pack B = 484-pin Ball-Grid Array (approximate) Maximum processor and CSI bus frequency Memory Size (K bytes) (MHz) Sales Offices Zylogic Semiconductor Corporation 1460 NewCentury Hote
® Zylogic ZE5 Configurable System-on-Chip Family CONTENTS OVERVIEW ...............................................................3 8032 "TURBO" MICROCONTROLLER .........................5 Programmable I/O Ports.....................................5 UART ..................................................................5 Timers.................................................................6 Interrupts ............................................................6 Data Pointers..............................
Zylogic ZE5 Configurable System-on-Chip Platform Six Global Buffers.............................................54 Clock and Global Signal Stopping....................54 PINOUT DIAGRAMS AND TABLES ............................. 79 Available Packages and Package Codes ........ 79 Footprint-Compatibility ..................................... 79 Available PIOs by Package.............................. 79 128-pin Thin Plastic Quad Flat Pack, top view (Package Code=L) ...........................................
ZYLOGIC ZE5 SWITCHING CHARACTERISTIC GUIDELINES ...........................................................95 ORDERING INFORMATION...................................... 119 SALES OFFICES ................................................... 119 General ZE5 Timing Characteristics ................95 JTAG Interface Timing Characteristics ............96 Pin-to-Pin Guaranteed Timing Specifications ..96 Memory Interface Unit (MIU) Timing Characteristics..................................................
