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Non linearity of C
oss
results in longer
minimum dead time for SJ FET in ZVS
CoolMOS™ P6 Cascode GaN
Vgs_ls
Vds_ls
Id_ls
50V
V
gs
=10 V, I
d
=2 A, R
g
=10 ohm
T
delay
SJ FET High capacitance at low voltage results
in 5-6x longer delay time (110 nsec vs 20
nsec)and therefore longer required deadtime
which increases RMS current and therefore
conduction losses. The higher the frequency
the more the losses
110 nSec
20 nSec
2d
9
14.04.2016 Copyright © Infineon Technologies AG 2016. All rights reserved.