Professional Education Seminar S17 Practical Application of 600 V GaN HEMTs in Power Electronics Monday March 16, 2015 8:30 – 12:00 Eric Persson, GaN Applications
Seminar Outline Limitations of today‟s 600 V Silicon Topologies where superjunction performs well Topologies where superjunction application is limited GaN HEMT characteristics – Depletion-mode, cascode, enhancement-mode – GaN applied to hard and soft-switching topologies Gate drive considerations for GaN PFC Application examples – Standard boost, dual boost, totem-pole bridgeless LLC converter example ZVS phase-shifted full-bridge example Motor drive example APEC 2015 Seminar S17 2
What needs improvement? For same Rds(on), improve all the charge parameters: Reduce Coss nonlinearity – Nonlinearity makes timing and dv/dt control challenging Reduce Qoss (and therefore Eoss) magnitude Reduce Coss dissipation factor Improve body diode dynamic performance – Reduce/eliminate Qrr Reduce gate charge All of the above at affordable cost APEC 2015 Seminar S17 3
Topologies where superjunction works well Unipolar current flow, hard or soft-switched Two-transistor forward – Hard switched, partial valley switched Boost PFC – CCM or CrCM Flyback – Hard switched, partial valley switched Why? – Superjunction has low Rds(on)*Eoss figure of merit – Body diode performance is not important APEC 2015 Seminar S17 4
2-Transistor Forward Converter (2TF) Vin APEC 2015 Seminar S17 5
2TF voltage and current waveforms Ref: Thierry Sutto, “2 switch forward current mode converter,” ON semi app note AND8373/D APEC 2015 Seminar S17 6
2TF FET turn-on loss measurement Ref: Thierry Sutto, “2 switch forward current mode converter,” ON semi app note AND8373/D APEC 2015 Seminar S17 7
2TF FET turn-on loss analysis This accounts for the “crossover” loss – Where the transistor is supporting simultaneous V and I What is missing? This suggests that if Δt goes to 0, Turn-on loss = 0 Ref: Thierry Sutto, “2 switch forward current mode converter,” ON semi app note AND8373/D APEC 2015 Seminar S17 8
What about the Eoss of the FET itself? Vd SiC Schottky Simplified Schematic iD Vd v DS t Io i D t Note: This is not Qrr vDS iG Vd DF RG Cak PLOSSt C gd1 C ds VGG t 0 IO C gs Current Commutation Qsw Discharge Equivalent Circuit APEC 2015 Seminar S17 9
2TF FET turn-off loss Turn-off losses limited entirely by gate drive – If you can turn-off the gate extremely fast, get ZVS Ref: Thierry Sutto, “2 switch forward current mode converter,” ON semi app note AND8373/D APEC 2015 Seminar S17 10
2 Transistor Forward Summary This is a unipolar topology – Superjunction already works well – Body diode performance is unimportant Switch losses are dominated by: – – – – Conduction Turn-on speed Eoss Turn-off speed Possible switch improvements – For a given Rds(on): – Reduced Eoss (stored energy in device Coss) – Reduced Qg to enable faster switching APEC 2015 Seminar S17 11
Flyback Converter Avalanche risk Vin IL Vds Vgs APEC 2015 Seminar S17 12
Flyback turn-on timing is critical Eoss dissipated proportional to Vds2 Strong dependence on timing turn-on to waveform – Turning on at peak versus valley – big difference in Eoss Vds Vds Iin Iin Vgs Vgs APEC 2015 Seminar S17 13
Flyback Summary This is a unipolar topology – Superjunction already works well – Body diode performance is unimportant – Avalanche or overvoltage capability likely necessary Switch losses are dominated by: – – – – Conduction Turn-on speed Eoss (valley switching can minimize loss) Turn-off speed Possible switch improvements – For a given Rds(on): – Reduced Eoss (stored energy in device Coss) – Reduced Qg to enable faster switching APEC 2015 Seminar S17 14
Standard boost PFC SB typically superjunction DB SiC Schottky for lowest loss Can achieve >96% efficiency REF: L. Huber, Y. Jang, M. Jovanovic, “Performance Evaluation of Bridgeless PFC Boost Rectifiers,” IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO.
Standard boost PFC Typical operating frequency <70 kHz – Keep fundamental and 2nd harmonic below 150 kHz EMI – Increasing frequency increases switching loss Control mode typically Continuous Conduction Mode – CCM balances ripple current losses and switching loss Can be operated Discontinuous or Critical mode – Much higher ripple current – But ZVS or near ZVS possible, much lower switching loss Either way, dominant loss is input bridge rectifier – 1-2% total efficiency loss due to input bridge
Standard boost PFC summary This is a unipolar topology – Superjunction already works well – Body diode performance is unimportant Switch losses are dominated by: – – – – Conduction (especially severe for high ripple CrCM and DCM) Turn-on speed Eoss (only for CCM) Turn-off speed Possible switch improvements – For a given Rds(on): – Reduced Eoss (stored energy in device Coss) – Reduced Qg to enable faster switching APEC 2015 Seminar S17 17
What about bridgeless PFC topologies? Dual boost – semi bridgeless S1 S2 commonly superjunction, D1 D2 SiC Ref: A. F. Souza and I. Barbi, “High power factor rectifier with reduced conduction and commutation losses,” in Proc. Int. Telecommunication Energy Conf., Jun. 1999, pp. 8.1.1–8.1.5.
Dual boost PFC summary This is a unipolar topology – Superjunction already works well – Body diode performance is unimportant Switch losses are dominated by: – – – – Conduction (especially severe for high ripple CrCM and DCM) Turn-on speed Eoss (only for CCM) Turn-off speed Possible switch improvements – For a given Rds(on): – Reduced Eoss (stored energy in device Coss) – Reduced Qg to enable faster switching Tradeoff: eliminate 1 diode drop, add an entire boost stage APEC 2015 Seminar S17 19
Why not totem-pole PFC with superjunction? Hard-switched half-bridge requires good body-diode REF: J. C. Salmon, “Circuit topologies for PWM boost rectifiers operated from 1-phase and 3-phase ac supplies and using either single or split dc rail voltage outputs,” APEC, Mar. 1995, pp. 473–479.
VSW = VDS(Q2) Hard-switched half-bridge Q1 IL 0 IQ2 t IL VSW IQ1 This is Q1 Eoss.
Summary: topologies with limited superjunction use Bipolar current flow topologies – Anywhere diode recovery is important Half-bridge hard-switching – Totem-pole bridgeless boost CCM (except line polarity switch) – Inverters, motor drives Half-bridge soft-switching or resonant? Depends… – Limited frequency range – Risk of hard-switching – Frequency dependent losses in Qoss APEC 2015 Seminar S17 22
GaN High Electron Mobility Transistor (HEMT) Depletion-mode basic HEMT – Normally-on is a problem for power electronics 2 methods to achieve normally-off – Cascode – Enhancement-mode GaN cascode characteristics GaN enhancement-mode characteristics GaN application summary – Hard-switching – Soft-switching & resonant APEC 2015 Seminar S17 23
GaN High Electron Mobility Transistor (HEMT) Depletion-mode (normally-on) HEMT Si substrate for low cost Normally-on potential problem for power electronics Ref: Jones, E.A.; Wang, F.; Ozpineci, B., "Application-based review of GaN HFETs," Wide Bandgap Power Devices and Applications (WiPDA) 2014, pp.24-29, 13-15 Oct.
Depletion-mode HEMT Normally-on – – – – Essentially a resistor that can be turned-off with -gate bias Potential issues with power-up and power-down Requires additional master enable switch Requires negative gate drive Low area specific on-resistance Bi-directional conduction – No intrinsic body diode Can be made bi-directional blocking Lateral device – monolithic integration possibilities APEC 2015 Seminar S17 25
Cascode Provides Normally-OFF Function Native d-mode GaN HEMT + LV Si FET in cascode – Rds(on) is compromised to shift threshold positive Cascode has easy gate drive Cascode includes excellent body diode 2-chip solution no more difficult than IGBT Almost zero “Miller Effect” D – C dv/dt immunity – Enables turn-off ZVS in almost any topology Depletion-Mode GaN HEMT Low Voltage Si MOSFET G Hybrid Semiconductor Device, US Pat.
Cascode Conduction Modes Ref: Xiucheng Huang, Fred C.
Body diode reverse-recovery >100x lower Qrr for GaN cascode GaN cascode switch 10 A/div Superjunction APEC 2015 Seminar S17 28
Comparing GaN cascode to superjunction 1st Generation GaN cascode Parameter GaN cascode Equivalent SJ Package 6x8 mm PQFN 8x8 mm PQFN Vdss 600 V 650 V Rdson typ 25°C 135 mΩ 115 mΩ Rdson typ 125°C 225 mΩ 230 mΩ GaN 1.67x; SJ 2x Qg (10V Vgs, 480V Vds) 8.8 nC 35 nC GaN ~4X lower than SJ Qrr (100A/µs, 25°C) 49 nC 6,400 nC GaN >100X lower than SJ Coss (400V) 47 pF 53 - 579 pF Energy vs time equivalent Rθ J-C (°C/W) 1.65 1.
Turn-on waveform, 135 mΩ (typ) cascode Hard-switching Rg = 2Ω.
GaN HEMT Safe Operating Area Measured destruct current >2x higher than calculated thermal limit 100 μs Drain Current, ID (A) 10 1 ms 10 ms 1 Experimental data from 190 mΩ max cascode prototype 0.
GaN performance interdependent on package Two key factors for minimizing losses: – Minimize GaN – Si interconnect inductance – Eliminate common-source inductance with Kelvin connection REF: Z. Liu, X. Huang, FC Lee, Q.
Die-on-die cascode construction Minimizes parasitic impedance between HEMT and FET – Faster switching transitions, less ringing and overshoot D Depletion-Mode GaN HEMT LV Si MOSFET mounted on Source pad of GaN on Si die Low Voltage Si MOSFET G S US Pat. No.
E-mode GaN HEMT Structures a) P-gate enhancement-mode b) P-gate enhancement-mode (gate injection) Ref: Jones, E.A.; Wang, F.; Ozpineci, B., "Application-based review of GaN HFETs," Wide Bandgap Power Devices and Applications (WiPDA) 2014, pp.24-29, 13-15 Oct.
Enhancement-Mode HEMT (Gate Injection) off Ref: http://www.semicon.panasonic.co.jp/en/news/contents/2013/apec/panel/APEC2013_GaN_FPD_WEB.
Gate Characteristics (Enhancement Mode) Typical non-insulated gate characteristic – Gate injection uses small DC current (e.g. 10 mA) Ref: Jones, E.A.; Wang, F.; Ozpineci, B., "Application-based review of GaN HFETs," Wide Bandgap Power Devices and Applications (WiPDA) 2014, pp.24-29, 13-15 Oct.
Output Characteristics (Enhancement Mode) HEMT turns back ON when drain goes below G, S Ref: Jones, E.A.; Wang, F.; Ozpineci, B., "Application-based review of GaN HFETs," Wide Bandgap Power Devices and Applications (WiPDA) 2014, pp.24-29, 13-15 Oct.
Reverse Bias Diode-Like Behavior + Vg1 - Equivalent Circuit when Vg = 0 D G + Vg2 - VGS’ = VD’S’ D D’ G G S S S’ S’ = drain acting as source in reverse bias D’ = source acting as drain in reverse bias APEC 2015 Seminar S17 38
Forward and Reverse I-V Characteristics HEMT eventually saturates at very high current Ref: http://www.semicon.panasonic.co.jp/en/news/contents/2013/apec/panel/APEC2013_GaN_FPD_WEB.
GaN, superjunction, (& SiC) transfer curves Cascode superjunction and SiC ~135 mΩ typical E-mode GaN (non GIT) ~50mΩ (135 mΩ @ 150°C) Transfer curve E-mode GaN Cascode GaN 10 SiC SJ 1 ID (A) 0.1 0.
Comparing GaN vs SJ Qoss REF: M. Treu, E. Vecino, M. Pippan, O. Häberlen, G. Curatola, G. Deboy, M. Kutschak, U.
Comparing Coss, Qoss, Eoss GaN vs SJ Blue = superjunction Red = e-mode HEMT Both ~70 mΩ max Rds(on) APEC 2015 Seminar S17 42
Comparing GaN vs superjunction turn-off LLC topology looking at low-side switch – 400 V bus, 2 A – Same Rds(on) Cascode GaN Superjunction Vds Vgs Vds Vgs Id Id APEC 2015 Seminar S17 43
Avalanche and overvoltage Superjunction has junction with avalanche capability – Useful in circuits with unclamped inductive energy (flyback) GaN has no junction, no avalanche behavior – GaN ultimately breaks down destructively at ~2x rating – Overvoltage spikes are allowed depending on supplier GaN is best suited for half-bridge topology – Fast body diode helps to mitigate overvoltage spikes – Overvoltage spikes are clamped to bus – With proper design, no risk of breakdown APEC 2015 Seminar S1
GaN Device Summary Both cascode and enhancement mode – compared to superjunction: Provides MUCH lower Qrr (zero for e-mode) – Enables use of efficient half-bridge topologies Provide smaller, more linear Qoss – Reduces deadtime in resonant and ZVS circuits Provide lower gate charge Qg – Lower gate drive power and faster switching speed Eoss not much difference Does not have avalanche behavior – Does have overvoltage capability APEC 2015 Seminar S17 45
Applications of GaN APEC 2015 Seminar S17 46
Gate Drive Cascode – standard Si gate drivers work – – – – – Vgs(th) is potential issue Common Source Inductance is a concern as always C dv/dt induced gate currents Kelvin gate-source connections Advantages of floating gate drive APEC 2015 Seminar S17 47
Gate drive challenges for low threshold devices DC Bus DC Bus L Isolated L Isolated ? Common Source Inductance distorts Vgs Kelvin source connection eliminates CSI …BUT can cause system grounding problems for driver APEC 2015 Seminar S17 48
Isolated gate drive + Kelvin source connection DC Bus DC Bus L Isolated L Isolated ? Isolating both high and low-side drivers solves system ground bounce issues which can affect current sense and logic ground APEC 2015 Seminar S17 49
Gate drive for gate injection REF: T. Morita, H. Hanada, S Ujita, M Ishida, T. Ueda, “99.3% Efficiency Boost-up Converter for Totem-pole Bridgeless PFC Using GaN Gate Injection Transistors,” Proc.
Gate drive summary Cascode GaN: – Standard FET gate driver compatibility – Lower Qg for given current-handling capability – ZVS turn-off easier to achieve Enhancement-mode GaN – – – – – Low threshold, noise sensitivity, negative drive can help Tighter limits on Vgs Very low Qg Kelvin source connection mandatory Floating driver helpful especially at higher power APEC 2015 Seminar S17 52
Totem-Pole PFC Full-Bridge High Frequency Half-Bridge This half-bridge is GaN cascode Q1 60Hz Polarity Switch Q3 This half-bridge is superjunction DC Bus AC LINE EMI Filter Q2 APEC 2015 Seminar S17 Q4 53
Totem-Pole PFC Full-Bridge 2.
Totem-Pole PFC Full-Bridge Input 230 VAC Output 400 VDC, 6.
Totem-Pole PFC full-bridge performance >99% efficiency from 18-70% load Measured Efficiency - PFC, VIN=230VAC 99.4 99.2 Efficiency (%) 99.0 98.8 45kHz 65kHz 98.6 98.4 98.2 0 500 1000 1500 2000 2500 3000 POUT (W) Complete Power Stage.
Totem Pole PFC No diode drops – only switch conduction voltage Very high efficiency possible >99% Lower component count than other bridgeless topologies Topology is enabled by GaN HEMT – Traditional Si FETs have too much body-diode Qrr Large recovery currents and high losses Topology is Intrinsically bi-directional power flow – Can also be used in inverter/UPS applications APEC 2015 Seminar S17 57
Totem Pole PFC Future MHz ZVS – still achieving 99% efficiency Multiphase architectures to minimize ripple Digital control to optimize performance & efficiency Ref: Zhengyang Liu, Fred C. Lee, QiangLi, “Digital Control for MHz Totem-pole PFC Rectifier,” CPES PMC Review, Mar.
LLC Resonant DC-DC Popular topology today using superjunction Frequency range <200 kHz typically Caution required to prevent hard-switching APEC 2015 Seminar S17 59
LLC typical waveforms and circuit APEC 2015 Seminar S17 60
GaN enables shorter deadtime vs SJ @ 1MHz Shorter deadtime lowers rms current I2 Primary I2 Secondary Gate Drive GaN 3.84A2 48.0A2 0.24W Superjunction 4.93A2 64.6A2 1.88W Difference +28.3% +34.
Nonlinear Qoss Charge Affects Deadtime 500 450 3.
Cascode Charge Balance During ZVS Turn-ON Improper charge balance results in loss of ZVS Properly balanced Cascode achieves full ZVS Significant energy loss No energy loss IL Vsw VDS-Si X. Huang, W. Du, Z. Liu, F. C. Lee, and Q.
Cascode Charge Balance During ZVS Turn-OFF Improper charge balance results in Si avalanche Properly balanced Cascode no avalanche, full ZVS Significant energy loss No energy loss Avalanche VDS-Si X. Huang, W. Du, Z. Liu, F. C. Lee, and Q.
ZVS phase-shifted full-bridge ZVS over most of power range except light-load Current-doubler output effective for 12 V and below APEC 2015 Seminar S17 65
ZVS phase-shifted full-bridge 1 kW 380 V to 12 V 350 kHz 120 W/in3 APEC 2015 Seminar S17 66
ZVS phase-shifted full-bridge Waveforms at 50% load APEC 2015 Seminar S17 67
ZVS phase-shifted full-bridge efficiency Efficiency vs Percentage Load 97 96 380V to 12V fsw = 350 kHz 95 94 93 92 91 90 Load Efficiemcy 10% 89.5% 20% 94% 40% 96.1% 50% 96.4% 80% 96.3% 100% 95.
Efficiency vs Frequency at half-load Comparing GaN cascode vs superjunction Freq [Khz] Efficiency_GaN [%] Efficiemcy_SJ [%] 100 96.7 96.5 200 96.5 96.2 300 96.4 95.4 350 96.3 95 400 95.9 94 450 500 95.6 95.4 97 96.5 96 95.5 Efficiency GaN efficiency 95 SJ efficiency 94.5 94 93.
Why GaN for Motor Drive Applications? Switching speed is not necessarily a key issue for drives: Typically want dv/dt <6V/ns (GaN can switch >10x faster) – I=C dv/dt currents in motor windings can result in failures – Corona and partial-discharge creates ozone and erodes insulation – Common-mode currents forced through bearings, eroding races Yet customers still want higher efficiency, increased density Compressor drives have even more constraints: – Very low leakage current mandates small Y-cap va
Typical Compressor Drive Today LINE INPUT BIAS POWER SUPPLY EMI FILTER INPUT RECTIFIER CONTROL & PWM AC MOTOR GATE DRIVERS DC BUS CAP OUTPUT INVERTER APEC 2015 Seminar S17 71
Conduction Voltage for Same Footprint Size Comparing Conduction voltage of IGBT vs FET (measured data) 3.0 2.5 2.0 Vds or Vce (Volts) 1.5 1.0 0.5 0.0 IRGR4045D 0.8Ω Si -0.5 0.16Ω GaN -1.0 -1.5 -2.0 -2.5 -3.
Total Power Loss Summary (per switch) 1.60 1.40 Watts loss @ Iout = 1A rms 1.20 1.00 conduction turn-off 0.80 turn-on Fixed 0.60 0.40 0.20 0.
Cascode GaN dv/dt control via Gate Modulation 2A Turn on 2A Turn off 50ns/div 100ns/div Vsw Vgs Vgs 3.7V/ns 3.
GaN HEMT Short-Circuit Capability Initial devices are high-gain – limited SCSOA – Typically ~ 1 µs @ 300V Likely tradeoff between gain and SCSOA similar to IGBTs Ref: Xing Huang; Dong Young Lee; Bondarenko, V.; Baker, A.; Sheridan, D.C.; Huang, A.Q.; Baliga, B.J., "Experimental study of 650V AlGaN/GaN HEMT short-circuit safe operating area (SCSOA)," Proc. ISPSD pp.
Summary GaN HEMTs offer performance improvements for power electronic applications – Benefits are strongly topology-dependent – Just dropping GaN into existing circuit may show little benefit Half-bridge topology is good match for GaN – Half-bridge requires good dynamic reverse conduction – Both cascode and e-mode GaN devices benefit half-bridge Higher efficiency at same frequency – By use of better topologies i.e.
Questions?
References 1) 2) 3) 4) 5) 6) 7) 8) 9) Alex Lidow, Johan Strydom, Michael de Rooij, David Reusch, “GaN Transistors for Efficient Power Conversion, 2nd Edition,” Wiley, ISBN: 978-1-118-84476-2, Sept. 2014 Fedison, J.B.; Fornage, M.; Harrison, M.J.; Zimmanck, D.R., "Coss related energy loss in power MOSFETs used in zero-voltage-switched applications," APEC 2014, pp.150-156, 16-20 March 2014 Strydom, J.T.; van Wyk, J.D.; Ferreira, J.A.
