User`s guide

E-Prime User’s Guide
Appendix A: Timing Test Results
Page A-14
Microsoft 2 Button PS/2 Mouse (modified for use) –the Microsoft mouse was modified on the
left switch to parallel in a high-speed reed relay (see #3 above). An external o-scope probe was
wired to the opposite side of the relay so that the TS could verify and timestamp when the mouse
switch device was activated (i.e., when the switch was actually closed).
BSOFT Engineering, Passive Interface Board PIB-110 – Two PIB-110 interface boards were
used to wire TTL lines between the TS and ES. The boards contain a DB-37 input connector and
then passively split out all 37 lines into 2 rows of screw terminal headers.
Test Methods
1. Clock Bin Test – In this test, the ES machine continuously reads the E-Prime real-time clock
for a preset period of time (e.g., 10 seconds). It then subtracts the difference between
consecutive clock-read values to determine if any type of delay (e.g., perhaps caused by the
operating system or some other running application) occurred between the clock reads. If no
delay occurred, the values should either be the same (i.e., multiple reads during the same
millisecond) or different by just 1ms. Any difference greater than 1ms is a potential timing error.
The delays are grouped into bins based on the duration of the delay. External hardware is used
to ensure that the test ran for the expected amount of time (e.g., to ensure that the real-time clock
was never paused or halted).
2a. Fixed Duration Clock Test – In this test, the ES machine toggles a single bit connected
directly to the TS in order to produce either a fixed or varying duration square wave. The TS
timestamps each bit transition observed, and reports the results. A sample table of results for the
fixed duration tests (run at 1, 10, 100, and 1000ms durations) is shown below.
ACTUAL DURATION BY EXPECTED FIXED DURATION
Expected Fixed Delay (ms)
1 10 100 1000 10000 Grand Total
Average of ACTUAL
1.019 9.999 99.991 999.910 9998.804 N/A
StdDev of ACTUAL
0.165 0.123 0.149 0.254 0.155 N/A
Min of ACTUAL
0.776 9.818 99.417 999.334 9998.604 0.776
Max of ACTUAL
1.933 10.259 101.528 1001.337 9999.069 9999.069
N (Num of Intervals)
1000 1000 1000 100 10 3110
ABSOLUTE TIMING ERROR BY FIXED INTERVAL
Fixed Interval (ms)
1 10 100 1000 10000 Grand Total
Average of ABS ERROR
0.137 0.120 0.130 0.171 1.196 0.134
StdDev of ABS ERROR
0.095 0.026 0.074 0.208 0.155 0.100
Min of ABS ERROR
0.064 0.060 0.047 0.001 0.932 0.001
Max of ABS ERROR
0.933 0.259 1.528 1.337 1.396 1.528
N (Num of Intervals)
1000 1000 1000 100 10 3110
2b. Varying Duration Clock Test – This test is the same as #2a, but the durations used are
incrementing delays of 1, 2, and 3ms as well as delays incrementing by prime numbers. Sample
results are shown below.