User's Manual

Functional Description
1-2 044-05210 Rev. A
from this block: control data and signal data. The control data determines parameters such as
channel frequencies, signal ramp-up/ramp down and transmit power level. These functions are
implemented in a Field Programmable Gate Array (FPGA).
1.3.2.2 Digital Up Converter (DUC)
The DUC modulates individual symbol streams from the signal data stream on to baseband carriers
and applies root-raised cosine channel filtering. This function is implemented on an Application-
Specific Standard Product (ASSP).
1.3.2.3 Crest Factor Reduction (CFR)
The CFR function is implemented in the FPGA. The CPR varies the DUC signals to reduce the peak-
to average power of the transmit signal to allow the P-Mod to operate with higher efficiency ensuring
the transmit signals stay in the occupied bandwidth/spectral mask limits.
1.3.2.4 Data Interpolation (INT)
The interpolation function, which is implemented in the FPGA, changes the sampling rate up to 92.16
Msps.
1.3.2.5 Digital Predistortion (DPD)
The DPD function, which uses an ASSP DPD engine, and a Digital Signal Processor (DSP),
processes the forward path signal to compensate for the non-linearities in the forward path. The DPD
function ensures that the transmitter operates at the correct power level over variations in supply
voltage, load impedance, temperature and aging.
The DPD function also provides compensation for imperfections in the AUC such as differential delay,
I-Q amplitude and phase balance and DC offset/carrier leakage. the linearisation lock function
monitors the operation of the signal and turns off the transmitter if the system is not functioning
correctly. The digital output signal from the DPD engine is converted back to an analog signal in a
high-speed digital-to-analogue converter (DAC).
1.3.2.6 Analog Up Converter (AUC)
The AUC uses a direct-conversion architecture (I-Q modulator) to transform the I-Q baseband signals
from the DPD up to the operating RF frequency.
1.3.2.7 Observation Path (OBS)
The OBS act as a high performance radio receiver tuned to the RF transmit frequency. The OBS
converts the sampled RF transmit signal to a VHF intermediate frequency where it is sampled by a
high-speed analogue-to-digital converter (ADC). The output of the ADC is fed to the DPD block,
compared with the drive signal and then used to update the parameters in the DPD algorithms
running on the DSP.
1.3.2.8 Clock Module
The FPGA high-speed serial interface (SerDes) extracts a timing clock from the incoming data
stream, the transmit frequency stability depends on the accuracy of the incoming input signal. The
recovered clock is used to synchronize a crystal oscillator used as a clean frequency reference for the
timing functions on the TRx board (RF LOs, DAC and ADC clocks, Tx, Rx and lineariser signal
processing clocks).
The reference is used as a direct reference for the RL local oscillators. Except for the digital clocks,
the reference is passed to a PLL VCO, which is then subdivided. All RF PLLs include lock-detect
signals to allow the transmitter to be turned off if there is a fault with a PLL.