User's Manual

USER MANUAL
Page. 12
10.1 SDIO Pin Description
The module supports SDIO version 2.0 for 4-bit modes (100 Mbps), and high speed 4-bit (50
MHz clocks – 200 Mbps). It has the ability to stop the SDIO clock and map the interrupt
signal into a GPIO pin. This ‘out-of-band’ interrupt signal notifies the host when the WLAN
device wants to turn on the SDIO interface. The ability to force the control of the gated
clocks from within the WLAN chip is also provided.
 Function 0 Standard SDIO function (Max BlockSize / ByteCount = 32B)
 Function 1 Backplane Function to access the internal System On Chip (SOC) address
space (Max BlockSize / ByteCount = 64B)
 Function 2 WLAN Function for efficient WLAN packet transfer through DMA (Max
BlockSize/ByteCount=512B)
11. Host Interface Timing Diagram
11.1 Power-up Sequence Timing Diagram
The module has signals that allow the host to control power consumption by enabling or
disabling the Bluetooth, WLAN and internal regulator blocks. These signals are described
below. Additionally, diagrams are provided to indicate proper sequencing of the signals for
carious operating states. The timing value indicated are minimum required values: longer
delays are also acceptable.
※ WL_REG_ON: Used by the PMU to power up the WLAN section.
When this pin is high, the regulators are enabled and the WLAN section is out of reset.
When this pin is low the WLAN section is in reset.
※ BT_RST_N: Low asserting reset for Bluetooth and FM only.
This pin has no effect on WLAN and does not control any PMU functions.
This pin must be driven high or low (not left floating).