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ManualsBrandsPololu ManualsInfrared Range FindersToF Range Finder Sensor Breakout Board w/ Voltage Regulator - VL53L1X
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DocID031281 Rev 2 19/35
VL53L1X Control interface
35
4 Control interface
This section specifies the control interface. The I
2
C interface uses two signals: the serial
data line (SDA) and serial clock line (SCL). Each device connected to the bus uses a unique
address and a simple master/slave relationships exists.
Both SDA and SCL lines are connected to a positive supply voltage using pull up resistors
located on the host. Lines are only actively driven low. A high condition occurs when the
lines float and the pull up resistors pull them up. When no data are transmitted both lines are
high.
Clock signal (SCL) generation is performed by the master device. The master device
initiates data transfer. The I
2
C bus on the VL53L1X has a maximum speed of 400 kbits/s
and uses a device address of 0x52.
Figure 11. Data transfer protocol
Information is packed in 8-bit packets (bytes) always followed by an acknowledge bit, Ac for
VL53L1X acknowledge and Am for master acknowledge (host bus master). The internal
data are produced by sampling SDA at a rising edge of SCL. The external data must be
stable during the high period of SCL. The exceptions to this are start (S) or stop (P)
conditions when SDA falls or rises respectively, while SCL is high.
A message contains a series of bytes preceded by a start condition and followed by either a
stop or repeated start (another start condition but without a preceding stop condition)
followed by another message. The first byte contains the device address (0x52) and also
specifies the data direction. If the least significant bit is low (that is, 0x52) the message is a
master-write-to-the-slave. If the LSB is set (that is, 0x53) then the message is a master-
read-from-the-slave.
Figure 12. VL53L1X I
2
C device address: 0x52
All serial interface communications with the camera module must begin with a start
condition. The VL53L1X module acknowledges the receipt of a valid address by driving the
SDA wire low. The state of the read/write bit (LSB of the address byte) is stored and the next
byte of data, sampled from SDA, can be interpreted. During a write sequence, the second
byte received provides a 16-bit index which points to one of the internal 8-bit registers.