Data Sheet

UM10204 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
User manual Rev. 6 — 4 April 2014 9 of 64
NXP Semiconductors
UM10204
I
2
C-bus specification and user manual
3.1.2 SDA and SCL logic levels
Due to the variety of different technology devices (CMOS, NMOS, bipolar) that can be
connected to the I
2
C-bus, the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed
and depend on the associated level of V
DD
. Input reference levels are set as 30 % and
70 % of V
DD
; V
IL
is 0.3V
DD
and V
IH
is 0.7V
DD
. See Figure 38, timing diagram. Some
legacy device input levels were fixed at V
IL
= 1.5 V and V
IH
= 3.0 V, but all new devices
require this 30 %/70 % specification. See Section 6
for electrical specifications.
3.1.3 Data validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH
or LOW state of the data line can only change when the clock signal on the SCL line is
LOW (see Figure 4
). One clock pulse is generated for each data bit transferred.
3.1.4 START and STOP conditions
All transactions begin with a START (S) and are terminated by a STOP (P) (see Figure 5).
A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered
to be busy after the START condition. The bus is considered to be free again a certain
time after the STOP condition. This bus free situation is specified in Section 6
.
The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In
this respect, the START (S) and repeated START (Sr) conditions are functionally identical.
For the remainder of this document, therefore, the S symbol is used as a generic term to
represent both the START and repeated START conditions, unless Sr is particularly
relevant.
Fig 4. Bit transfer on the I
2
C-bus
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 5. START and STOP conditions
mba608
SDA
SCL
P
STOP condition
S
START condition