Data Sheet

UM10204 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
User manual Rev. 6 — 4 April 2014 33 of 64
NXP Semiconductors
UM10204
I
2
C-bus specification and user manual
Logic levels are slightly different also: TTL for SMBus: LOW = 0.8 V and HIGH = 2.1 V,
versus the 30 %/70 % V
DD
CMOS level for I
2
C. This is not a problem if V
DD
> 3.0 V. If the
I
2
C device is below 3.0 V, then there could be a problem if the logic HIGH/LOW levels are
not properly recognized.
4.2.2 Time-out feature
SMBus has a time-out feature which resets devices if a communication takes too long.
This explains the minimum clock frequency of 10 kHz to prevent locking up the bus. I
2
C
can be a ‘DC’ bus, meaning that a slave device stretches the master clock when
performing some routine while the master is accessing it. This notifies the master that the
slave is busy but does not want to lose the communication. The slave device will allow
continuation after its task is complete. There is no limit in the I
2
C-bus protocol as to how
long this delay can be, whereas for a SMBus system, it would be limited to 35 ms.
SMBus protocol just assumes that if something takes too long, then it means that there is
a problem on the bus and that all devices must reset in order to clear this mode. Slave
devices are not then allowed to hold the clock LOW too long.
4.2.3 Differences between SMBus 1.0 and SMBus 2.0
The SMBus specification defines two classes of electrical characteristics: low power and
high power. The first class, originally defined in the SMBus 1.0 and 1.1 specifications, was
designed primarily with Smart Batteries in mind, but could be used with other low-power
devices.
The 2.0 version introduces an alternative higher power set of electrical characteristics.
This class is appropriate for use when higher drive capability is required, for example with
SMBus devices on PCI add-in cards and for connecting such cards across the PCI
connector between each other and to SMBus devices on the system board.
Devices may be powered by the bus V
DD
or by another power source, V
Bus
(as with, for
example, Smart Batteries), and will inter-operate as long as they adhere to the SMBus
electrical specifications for their class.
NXP devices have a higher power set of electrical characteristics than SMBus 1.0. The
main difference is the current sink capability with V
OL
=0.4V.
• SMBus low power = 350 μA
• SMBus high power = 4 mA
• I
2
C-bus = 3 mA
SMBus ‘high power’ devices and I
2
C-bus devices will work together if the pull-up resistor
is sized for 3 mA.
For more information, refer to: www.smbus.org/
.