Data Sheet

1
2
3
4
5
6
18
17
16
15
14
13
24 23 22 21 20 19
7 8 9
10 11 12
AOUT 1
AISEN
AOUT 2
BOUT 2
BISEN
BOUT 1
GND
VINT
VM
VM
VCP
nFAULT
nE N BL / A E N BL
STE P / B EN BL
D IR / BPH A S E
M 0 / APH A S E
M 1
CO N FIG
AVREF
BVREF
VREFO
nS LEEP
BDEC A Y
AD E C A Y
GND
(PPAD)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
(PPAD)
nSLEEP
BDECAY
ADECAY
AOUT1
AISEN
AOUT2
BOUT2
BISEN
BOUT1
nENBL / AENBL
STEP / BENBL
DIR / BPHASE
VREFO
BVREF
AVREF
GND
VINT
VM
VM
VCP
nFAULT
CONFIG
M1
M0 / APHASE
DRV8834
www.ti.com SLVSB19D –FEBRUARY 2012–REVISED MARCH 2015
6 Pin Configuration and Functions
PWP Package
RGE Package
24-Pin HTSSOP
24-Pin VQFN
Top View
Top View
Pin Functions
PIN
EXTERNAL COMPONENTS
I/O DESCRIPTION
OR CONNECTIONS
NAME HTSSOP VQFN
POWER AND GROUND
21, 18, Both the GND pin and device PowerPAD
GND — Device ground
PPAD PPAD must be connected to ground
Connect to motor supply. A 10-µF (minimum)
VM 18, 19 15, 16 — Bridge A power supply
capacitor to GND is recommended.
Bypass to GND with 2.2-μF (minimum), 6.3-V
capacitor. Can be used to provide logic high
VINT 20 17 — Internal supply
voltage for configuration pins (except
nSLEEP).
May be connected to AVREF/BVREF inputs.
VREFO 24 21 O Reference voltage output
Do not place a bypass capacitor on this pin.
Connect a 0.01-μF, 16-V (minimum) X7R
VCP 17 14 O High-side gate drive voltage
ceramic capacitor to VM.
CONTROL (INDEXER MODE OR PHASE/ENABLE MODE)
Indexer mode: Logic low enables all outputs.
Phase/enable mode: Logic high enables the
nENBL/AENBL 10 7 I Step motor enable/Bridge A enable
AOUTx outputs.
Internal pulldown.
Indexer mode: Rising edge moves indexer to
next step.
STEP/BENBL 11 8 I Step input/Bridge B enable Phase/enable mode: Logic high enables the
BOUTx outputs.
Internal pulldown.
Indexer mode: Level sets direction of step.
Phase/enable mode: Logic high sets BOUT1
DIR/BPHASE 12 9 I Direction input/Bridge B Phase
high, BOUT2 low.
Internal pulldown.
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