Data Sheet

The SDOMX bit is set to 1, so the SDO (SPI data output) pin is assigned to RB3.
The T3CMX bit is set to 1, so the T3CKI (Timer3 clock input) pin is assigned to RC0.
The CCP2MX bit is set to 1, so the CCP2 input/output pin is assigned to RC1.
Clock selection
The P-Star is configured to automatically use the onboard 16 MHz crystal, which is also known as the primary
oscillator. The signal from the crystal goes to a PLL, which uses it to generate a 48 MHz signal for the CPU and
the peripherals. The CPU takes at least 4 cycles to execute a single instruction, so it can execute up to 12 million
instructions per second (12 MIPS).
The PCLKEN configuration bit is set to 0, so it is possible to shut down the primary oscillator and switch over to
the internal oscillator of the PIC microcontroller. However, without changing the FOSC<3:0> configuration bits,
it is not possible to clock the USB module from the internal oscillator. Also, without changing the FOSC<3:0>
configuration bits, it is not possible to send the signal from the internal oscillator through the PLL, so the
maximum CPU clock speed would be 16 Mhz (4 million instructions per second), which is three times slower
than the default.
Brown-out reset
The brown-out reset threshold on the P-Star is set to a nominal value of 2.85 V. The brown-out reset is enabled
by default, but it can be disabled in software by clearing the SBOREN bit in the RCON register. The low-power
brown-out reset circuit is also enabled, and will cause the microcontroller to reset at some point between 1.8 V
and 2.1 V.
Clearing the SBOREN bit will reduce the power consumption of the microcontroller and will allow it to continue
operating if VDD falls below 2.85 V. However, it will not be able to power up successfully from a voltage below
2.85 V, because SBOREN is set to 1 on power-up. Also, the microcontroller is not guaranteed to operate correctly
below 2.7 V without switching to a slower clock source.
Watchdog timer
The watchdog timer is disabled by default, but it can be enabled by setting the SWDTEN bit in the WDTCON
register. The watchdog postscaler is set to 1:256, so the watchdog timer’s period is about 1048 ms.
Read/write protection
The region of flash memory occupied by the bootloader is write-protected to prevent accidental corruption of
the bootloader. The lower 2 KB of the bootloader’s flash memory are readable and contain some useful data (as
described in Section 6.1), but the rest of the bootloader is read-protected.
Pololu P-Star 25K50 Micro User’s Guide © 2001–2017 Pololu Corporation
6. The P-Star 25K50 Bootloader Page 25 of 38