Data Sheet

DocID027112 Rev 4 21/50
LPS25HB FIFO
50
4.7 Bypass-to-FIFO mode
In Bypass-to-FIFO (F_MODE[2:0] in FIFO_CTRL (2Eh) set to '111'), the FIFO is in Bypass
mode until a trigger event occurs and the FIFO starts operating in FIFO mode. A trigger
event is based on the IA bit in INT_SOURCE (25h) and it is configured by
INTERRUPT_CFG (24h).
Figure 11. Bypass-to-FIFO mode
4.8 Retrieving data from FIFO
When the FIFO is enabled, FIFO data are read from PRESS_OUT_H (2Ah),
PRESS_OUT_L (29h), and PRESS_OUT_XL (28h) registers.
Each time data is read from the FIFO, the oldest data are placed in the PRESS_OUT_H
(2Ah), PRESS_OUT_L (29h) and PRESS_OUT_XL (28h) registers and both single-read
and read-burst operations can be used.
The reading address is automatically updated by the device and it rolls back to 28h when
register 2Ah is reached. In order to read all FIFO levels in a multiple byte reading, 96 bytes
(3 output registers by 32 levels) must be read.