Data Sheet

DocID027112 Rev 4 11/50
LPS25HB Mechanical and electrical specifications
50
2.3 Communication interface characteristics
2.3.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and T
OP
.
Figure 3. SPI slave timing diagram
Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
Table 6. SPI slave timing values
Symbol Parameter
Value
(1)
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on
characterization results, not tested in production.
Unit
Min Max
t
c(SPC)
SPI clock cycle 100 ns
f
c(SPC)
SPI clock frequency 10 MHz
t
su(CS)
CS setup time 6
ns
t
h(CS)
CS hold time 8
t
su(SI)
SDI input setup time 5
t
h(SI)
SDI input hold time 15
t
v(SO)
SDO valid output time 50
t
h(SO)
SDO output hold time 9
t
dis(SO)
SDO output disable time 50